Semiconductor Gate Electrode Segmentation for Non-Volatile Memory
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Solution Overview
Problem
Current semiconductor devices with non-volatile memory face challenges in improving performance and reliability, particularly in the design and manufacturing process of memory cells and MISFETs, where existing methods do not effectively optimize the gate electrode structure and insulation films for enhanced operational efficiency.
Innovation Solution
A method of manufacturing a semiconductor device involving the formation of specific gate electrode structures and insulation films, including a first and second gate electrode for memory cells and a dummy gate electrode for MISFETs, with metal silicide layers and charge accumulation insulation films, which allows for improved performance and reliability by optimizing the gate insulation and metal silicide layer formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate electrode structure is used for both memory cells and MISFETs, then the manufacturing process is simpler, but the performance and reliability of the semiconductor device cannot be optimized
Solution Approach 1:
The gate electrode structure is segmented into different types: a first gate electrode for memory cells with specific insulation films, and a second gate electrode for MISFETs with different insulation films. This segmentation allows each gate structure to be optimized for its specific function, improving overall device reliability while maintaining manufacturing feasibility through standardized processes.
Solution Approach 2:
Different gate electrode structures and insulation film configurations are applied to different regions of the semiconductor device. Memory cell regions receive gate electrodes with specific insulation films optimized for charge storage, while MISFET regions receive gate electrodes with insulation films optimized for transistor operation. This local quality approach ensures each region has the optimal structure for its intended function.
2Reliability
If the same insulation film structure is used for memory cells and MISFETs, then the manufacturing process is easier, but the operational efficiency and data holding capabilities cannot be enhanced
Solution Approach 1:
Insulation films are formed preliminarily in specific regions before gate electrode formation. A first insulation film is formed in the memory cell region before the first gate electrode, and a second insulation film is formed in the MISFET region before the second gate electrode. This preliminary action allows each insulation film to be optimized for its specific application while using standardized deposition processes.
Solution Approach 2:
Different insulation film parameters (material composition, thickness, dielectric constant) are used for memory cells versus MISFETs. The first insulation film in memory cells is designed with parameters optimized for charge accumulation and data holding, while the second insulation film in MISFETs is designed with parameters optimized for transistor operation. These parameter changes enable enhanced data holding capability while maintaining ease of manufacture through conventional film deposition techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the performance and reliability of semiconductor devices by optimizing the gate electrode structure and insulation films, leading to improved data holding capabilities and reduced voltage requirements for write and erase operations.
Implementation Method 1
a second gate insulation film having a charge accumulation portion in the inside is interposed between the second gate electrode and the semiconductor substrate
Implementation Method 2
a metal silicide layer is formed over the first semiconductor region and over the second semiconductor region
Data Source
AI summary
A control gate electrode and a memory gate electrode of a memory cell of a non-volatile memory are formed in a memory cell region of a semiconductor substrate, and a dummy gate electrode is formed in a peripheral circuit region. Then, n+-type semiconductor regions for a source or a drain of the memory cell are formed in the memory cell region and n+-type semiconductor regions for a source or a drain of MISFET are formed in the peripheral circuit region. Then, a metal silicide layer is formed over the n+-type semiconductor regions but the metal silicide layer is not formed over the control gate electrode, the memory gate electrode, and the gate electrode. Subsequently, the gate electrode is removed and replaced with the gate electrode for MISFET. Then, after removing the gate electrode and replacing it with a gate electrode for MISFET, a metal silicide layer is formed over the memory gate electrode and the control gate electrode.