FinFET Semiconductor Fins with SiGe Core and Triple SIT Process
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Solution Overview
Problem
Conventional methods face challenges in forming stable high atomic percentage germanium films for FinFET devices due to damage from wet and dry etching processes, and conventional sidewall image transfer (SIT) techniques are costly and difficult to implement for tight fin pitches required in advanced nodes like 7 nm and beyond.
Innovation Solution
A method involving the formation of semiconductor fins with an inner core of silicon germanium (SiGe) having a high germanium content and an outer shell of silicon or SiGe with low germanium content, using a triple SIT spacer process to create a pattern that prevents damage during etching and allows for precise fin formation with tight pitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high atomic percentage germanium films are formed using conventional methods, then the channel material performance is improved, but the films suffer significant physical damage during wet and dry etching processes
Solution Approach 1:
A protective sacrificial layer (such as silicon nitride or silicon oxide) is deposited over the high atomic percentage germanium channel layer before subsequent processing steps. This sacrificial layer prevents physical damage to the germanium during wet and dry etching processes by serving as a protective barrier that can be removed later without compromising the germanium channel integrity
Solution Approach 2:
The sacrificial layer acts as an intermediary between the etching processes and the high atomic percentage germanium channel. This intermediate layer absorbs the harmful effects of etching chemicals and plasma, allowing the germanium to remain protected while still enabling the necessary manufacturing processes to proceed
2Manufacturing precision
If conventional lithography patterning is used, then the manufacturing process is simple, but it cannot achieve the tight fin pitch required for 7 nm nodes and beyond
Solution Approach 1:
The patent transitions from planar 2D lithography patterning to 3D vertical patterning using self-aligned spacer formation. By depositing conformal spacer layers around mandrels and using vertical etching, the process achieves sub-10nm fin pitches that are beyond the capability of conventional lithography, effectively adding a vertical dimension to the patterning process
Solution Approach 2:
The patterning process is segmented into multiple discrete steps: forming mandrels, depositing first spacers, forming second spacers, and selective removal. This segmentation allows each step to be optimized independently and achieves the required precision through cumulative effect rather than relying on a single lithography exposure
3Manufacturing precision
If conventional SIT2 process is used to form tight pitch fins, then the fin pitch is reduced, but manufacturing costs increase and unwanted fin removal becomes difficult
Solution Approach 1:
The self-aligned spacer formation process is self-correcting and self-defining. Each spacer automatically aligns to the previous structure, eliminating the need for separate alignment steps and reducing manufacturing complexity. The process inherently defines the final fin positions without requiring additional cutting or removal steps, making unwanted fin removal unnecessary
Data Source
AI summary
A method of forming a semiconductor structure includes providing a semiconductor substrate, forming at least one precursor semiconductor fin from the semiconductor substrate, etching through at least a portion of the at least one precursor semiconductor fin to form at least one patterned precursor semiconductor fin having a gap therein. The at least one patterned precursor semiconductor fin includes a first vertical surface and a second vertical surface with the gap therebetween. In addition, the method further includes forming a semiconductor material in the gap of the at least one patterned precursor semiconductor fin, in which the first vertical surface and the second vertical surface laterally surround the semiconductor material, and transforming the at least one patterned precursor semiconductor fin into at least one semiconductor fin including the semiconductor material therein.