Gate-All-Around Source/Drain Isolation for DIBL and Leakage Control
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Solution Overview
Problem
Gate-all-around (GAA) devices face challenges such as drain-induced-barrier-lowering (DIBL) and increased residual leakage current due to direct contact between epitaxial source/drain structures and the substrate, which degrades their performance.
Innovation Solution
The method involves forming epitaxial source/drain features on a dielectric layer without direct contact with the substrate, using a sacrificial epitaxy structure that is later replaced by an inner spacer, thereby improving DIBL and leakage control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If epitaxial source/drain structures directly contact the substrate, then manufacturing is simpler, but drain-induced-barrier-lowering increases and leakage current increases
Solution Approach 1:
A dielectric layer is introduced as an intermediary between the epitaxial source/drain structures and the substrate. This dielectric layer prevents direct contact, thereby reducing drain-induced-barrier-lowering and improving leakage control while maintaining manufacturing feasibility through standard deposition processes.
Solution Approach 2:
The source/drain structure is segmented into distinct regions: the epitaxial source/drain feature, the dielectric layer underneath, and the substrate. This segmentation allows independent optimization of each layer's properties and functions, enabling better electrical isolation and reduced leakage current.
2Device complexity
If epitaxial source/drain structures directly contact the substrate, then device structure is simpler, but residual leakage current increases
Solution Approach 1:
The dielectric layer serves as a mediator that electrically isolates the epitaxial source/drain structures from the substrate, blocking the path for residual leakage current while adding minimal structural complexity to the overall device.
3Ease of manufacture
If epitaxial source/drain structures directly contact the substrate, then fabrication process is simpler, but DIBL increases
Solution Approach 1:
The dielectric layer acts as a spacer that physically separates the epitaxial source/drain structures from the substrate, reducing the electric field coupling between drain and source regions and thereby mitigating drain-induced-barrier-lowering effects.
4Reliability
If sacrificial epitaxy structure is used and replaced by inner spacer, then leakage control improves, but manufacturing complexity increases
Solution Approach 1:
A sacrificial epitaxy structure is formed in advance before the final source/drain epitaxial growth. This preliminary structure serves as a template or placeholder that defines the eventual source/drain region geometry, allowing precise control of the final structure while managing manufacturing complexity through staged fabrication.
Solution Approach 2:
The sacrificial epitaxy structure is temporarily formed, serves its purpose as a template, and then selectively removed or replaced by the inner spacer. This temporary structure enables precise patterning and control of the final source/drain regions, with the sacrificial material being discarded after fulfilling its templating function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance of GAA devices by reducing DIBL and improving leakage control, creating a continuous crystal surface for epitaxial growth and separating the source/drain features from the substrate, thus optimizing device performance.
Implementation Method 1
epitaxial source/drain features on a dielectric layer without direct contact with the substrate, using a sacrificial epitaxy structure
Data Source
AI summary
Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer including different semiconductor materials, and the fin comprises a channel region and a source/drain region; forming a dummy gate structure over the channel region of the fin and over the substrate; etching a portion of the fin in the source/drain region to form a trench therein, wherein a bottom surface of the trench is below a bottom surface of the second semiconductor layer; selectively removing an edge portion of the second semiconductor layer in the channel region such that the second semiconductor layer is recessed; forming a sacrificial structure around the recessed second semiconductor layer and over the bottom surface of the trench; and epitaxially growing a source/drain feature in the source/drain region of the fin.