Nanosheet Gate Architecture for Mixed-Vt Cell-Height Scaling
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Solution Overview
Problem
The semiconductor industry faces challenges in fabricating FinFET devices with nanowires or nanosheets at technology nodes below 3 nm due to difficulties in achieving multiple threshold voltages (Vts) and maintaining metal gate material integrity during the patterning process, particularly with wet over-etching leading to metal gate loss and varied patterning boundaries.
Innovation Solution
An etching back process using a sacrificial layer is employed to isolate multiple patterning gates with mixed Vts, allowing for the removal of the n-type work function layer from neighboring p-type device regions without metal gate material loss, thereby achieving high Vt control and uniformity in both n-type and p-type regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If wet over-etching is used to remove work function layers, then complete removal is achieved, but metal gate material loss occurs and patterning boundaries become varied
Solution Approach 1:
A sacrificial layer is introduced as an intermediary material between the work function layer and the metal gate. This sacrificial layer is selectively removed to expose the metal gate for work function layer removal, then restored to protect the metal gate during subsequent processing. The sacrificial layer acts as a temporary mediator that enables complete work function layer removal while preventing metal gate material loss.
Solution Approach 2:
The metal gate is restored with protective material before the work function layer removal process begins. This preliminary restoration action ensures that the metal gate is protected from etching damage before the harmful etching process occurs, allowing complete work function layer removal without metal gate material loss.
2Productivity
If cell height is reduced for scaling, then device density increases, but control over threshold voltage and material uniformity becomes difficult
Solution Approach 1:
The gate structure is segmented into distinct functional layers: the metal gate layer for charge storage, the gate dielectric layer for electrical isolation, and the sacrificial layer for process control. This segmentation allows each layer to be independently optimized and processed, enabling precise threshold voltage control even in scaled devices with reduced cell height.
Solution Approach 2:
The sacrificial layer serves as a mediator that enables precise control of the gate structure formation process. By using the sacrificial layer as a template and protective element, the metal gate and gate dielectric can be deposited with controlled thicknesses and uniformity, maintaining manufacturing precision despite reduced device dimensions.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes first channel nanostructures in a first device region and second channel nanostructures in a second device region. The first channel nanostructures are disposed between first and second dielectric fins. The second channel nanostructures are disposed between first and third dielectric fins. A gate dielectric layer is formed to surround each of the first and the second channel nanostructures and over the first, the second and the third dielectric fins. A first work function layer is formed to surround each of the first channel nanostructures. A second work function layer is formed to surround each of the second channel nanostructures. A first gap is present between every adjacent first channel nanostructures and a second gap present is between every adjacent second channel nanostructures.