High-k Gate Dielectric Self-Protective Layer for Etch Stop

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Solution Overview

Problem

In semiconductor manufacturing, particularly in FinFET devices, the challenge lies in accurately controlling the deposition and patterning processes for metal gate stacks, which can lead to improper etching of gate dielectric layers, resulting in deteriorated electrical performance due to the lack of effective protection during the replacement gate process.

Innovation Solution

A self-protective layer is formed on the gate dielectric layer using a phosphoric acid-based etching solution, which reacts with metal elements in the high-k dielectric layer to create a metal phosphate layer that prevents further etching and maintains the integrity of the gate dielectric, thereby protecting it during the patterning process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a replacement gate process is used to form metal gate stacks, then device performance can be improved, but the gate dielectric layer may be improperly etched due to lack of protection during patterning

Engineering Contradiction:
Improvedevice performanceVSAvoidetching damage to gate dielectric
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A protective layer is formed on the gate dielectric layer before the patterning process begins. This preliminary protective action ensures that the gate dielectric is shielded from etching damage during subsequent metal gate stack fabrication, allowing the replacement gate process to proceed without compromising dielectric integrity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The protective layer acts as an intermediary between the etching solution and the gate dielectric layer. It selectively protects the gate dielectric from harmful etching effects while allowing the patterning process to continue, thus mediating between the need for precise patterning and the need to preserve dielectric integrity

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If deposition and patterning processes are performed during gate fabrication, then metal gate stacks can be formed, but electrical performance deteriorates due to improper control of these processes

Engineering Contradiction:
Improvegate stack fabricationVSAvoidelectrical performance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The protective layer provides visual and physical feedback during the patterning process, indicating where etching should and should not occur. This feedback mechanism helps control the deposition and patterning processes more precisely, preventing electrical performance deterioration while maintaining ease of manufacture

Inventive Principle:
Principle #23Feedback

3Productivity

If the gate dielectric layer is exposed during patterning, then metal gate stacks can be formed, but the integrity of the gate dielectric deteriorates without protection

Engineering Contradiction:
Improvegate fabrication efficiencyVSAvoidgate dielectric integrity
Core Design Contradiction:
ProductivityVSStability of the object's composition

Solution Approach 1:

The protective layer is applied in advance before any exposure or patterning occurs. This preliminary protection allows the gate dielectric to be exposed and patterned efficiently without compromising its compositional integrity, thus maintaining both productivity and stability

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The self-protective layer effectively stops the etching process at the gate dielectric layer, ensuring its integrity and enhancing the electrical performance of the metal gate structure by preventing unintended etching, thus improving the reliability of the semiconductor device.

Implementation Method 1

A self-protective layer is formed on the gate dielectric layer using a phosphoric acid-based etching solution, which reacts with metal elements in the high-k dielectric layer to create a metal phosphate layer

Methodology Applied
Scientific EffectChemical reaction: Chemical Bonding

Implementation Method 2

A method for selectively etching a substrate is provided, in which a self-protective layer is formed on a high-k dielectric layer during an etching process

Methodology Applied
Scientific EffectEtching: Ablation

Data Source

PatentUS20240203740A1Self-protective layer formed on high-k dielectric layer
Publication Date: 2024.06.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240203740A1 patent drawing
  • US20240203740A1 patent drawing
  • US20240203740A1 patent drawing

AI summary

Semiconductor device structures having metal gate structures with tunable work function values are provided. In one example, a first gate structure and a second gate structure formed on a substrate, wherein the first gate structure includes a first work function metal having a first material, and the second gate structure includes a second work function metal having a second material, the first material being different from the second material, wherein the first gate structure further includes a gate dielectric layer, a self-protective layer having metal phosphate, and the first work function metal on the self-protective layer.