Hybrid Gate Dielectric Access Structure for 3D Memory Leakage Control
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Solution Overview
Problem
In vertical three-dimensional (3D) memory devices, there is a challenge in scaling down access devices while maintaining threshold voltage control and reducing current leakage, as design rules become smaller, and the variability of access current increases with more tiers, leading to lower fully depleted body threshold voltage and marginal cell storage capacitance.
Innovation Solution
A hybrid gate dielectric access device is introduced, featuring a multi-layer gate dielectric structure with a first and second dielectric layer material composition, where the second layer has a high thermal budget tolerance, suppresses Fowler-Nordheim tunneling, and provides a greater equivalent oxide thickness, achieving a smaller electric field without degrading underlap resistance, thus enabling higher threshold voltage and better conduction control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If design rules are scaled down to increase memory density, then memory capacity increases, but threshold voltage control deteriorates and current leakage increases
Solution Approach 1:
The gate dielectric is segmented into multiple layers with different material compositions (e.g., silicon oxide, silicon nitride, silicon oxynitride) and different functions. The first layer provides baseline insulation, while the second layer with higher fixed charge density specifically targets threshold voltage control, allowing each layer to optimize for its particular function rather than requiring a single layer to do everything
Solution Approach 2:
Different regions of the gate dielectric structure have different material properties tailored to local needs. The interface between the gate dielectric and channel region uses materials with specific fixed charge densities to locally enhance threshold voltage control where it is most needed, while other regions maintain general insulation properties
2Productivity
If access device dimensions are reduced to increase memory capacity, then memory scalability improves, but conduction control deteriorates
Solution Approach 1:
The invention changes the electrical parameters of the gate dielectric by selecting materials with different fixed charge densities and combining them in specific configurations. This allows tuning of the threshold voltage and conduction characteristics without changing the physical dimensions of the access device, enabling continued scaling while maintaining control
3Quantity of substance
If the number of tiers is increased to increase memory capacity, then memory density increases, but access current variability increases
Solution Approach 1:
The gate dielectric structure is designed in advance with specific material compositions and thicknesses to pre-compensate for the effects of increased tier count. By incorporating layers with appropriate fixed charge densities before device assembly and operation, the threshold voltage is pre-adjusted to account for the additional tiers, reducing variability in access current across different memory configurations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances access device conduction control, increases threshold voltage, and reduces current leakage in the 'off' state while maintaining charge storage retention, comparable to buried recessed access device architectures, and supports scalable and efficient vertical 3D memory designs.
Implementation Method 1
the second layer can tolerate a high thermal budget, suppress Fowler-Nordheim tunneling, and provide a greater, total equivalent oxide thickness
Data Source
AI summary
Systems, methods and apparatus are provided for a hybrid gate dielectric access device for vertical three-dimensional (3D) memory. The memory cell has a first horizontally oriented access device having a first source/drain region and a second source/drain region separated by a first channel region. The first access device is operatively controlled by a first gate. A hybrid gate dielectric separates the gate from the channel region and a horizontally oriented storage node coupled to the second source/drain region of the access device.