Array Substrate With Sandwich Pixel Electrodes For Storage Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing pixel pitch and aperture ratio in Advanced Super Dimension Switch (ADSDS) liquid crystal display panels lead to reduced storage capacitance, weakening the ability to drive liquid crystals and resulting in lower pixel voltage retention, image quality issues, and defects like flicker.
Innovation Solution
The array substrate design includes a base substrate with a thin film transistor and a common electrode, featuring two pixel electrodes – one below and one above the common electrode – both electrically connected to the drain electrode, with insulating layers in between to increase storage capacitance without increasing the risk of short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the distance between the pixel electrode and the common electrode is reduced to increase storage capacitance, then the storage capacitance increases, but the probability of short circuit between the pixel electrode and the common electrode increases
Solution Approach 1:
The patent introduces a third dimension by placing one pixel electrode above and another below the common electrode, transforming the traditional single-sided configuration into a three-dimensional sandwich structure. This dimensional change increases storage capacitance through multiple electrode pairs while maintaining safe distances to prevent short circuits.
Solution Approach 2:
The pixel electrode is segmented into two separate electrodes positioned on opposite sides of the common electrode. This segmentation allows each electrode to function independently with adequate spacing, eliminating the short circuit risk while collectively providing increased storage capacitance.
2Measurement precision
If the pixel pitch is reduced to increase resolution, then the resolution increases, but the storage capacitance decreases
Solution Approach 1:
By utilizing the third dimension (above and below the common electrode plane), the patent achieves increased storage capacitance without requiring larger pixel pitch. The vertical stacking of electrodes provides additional capacitance within the same planar footprint, enabling high resolution to be maintained.
Solution Approach 2:
The electrode structure is nested in a compact configuration where pixel electrodes are positioned on both sides of the common electrode, maximizing the use of available space within each pixel region and maintaining small pixel pitch while achieving sufficient storage capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the retention rate of pixel voltage, reduces undesirable defects such as flicker, and improves image quality by increasing storage capacitance while maintaining the aperture ratio.
Implementation Method 1
a first insulating layer provided between the second pixel electrode and the common electrode; and a second insulating layer provided between the common electrode and the thin film transistor
Implementation Method 2
a first pixel electrode and a second pixel electrode both electrically connected with the drain electrode of the thin film transistor. The first pixel electrode is provided below the common electrode and is insulated from the common electrode, and the second pixel electrode is provided above the common electrode and is insulated from the common electrode
Data Source
AI summary
Embodiments of the present disclosure disclose an array substrate, a liquid crystal display panel and a display device. The array substrate comprises a base substrate and a thin film transistor provided on the base substrate, and the thin film transistor comprises a gate electrode, an active layer, a source electrode and a drain electrode. The array substrate further comprises: a common electrode provided above the thin film transistor, and a first pixel electrode and a second pixel electrode both electrically connected with the drain electrode of the thin film transistor. The first pixel electrode is provided below the common electrode and is insulated from the common electrode, and the second pixel electrode is provided above the common electrode and is insulated from the common electrode.