Thin-Film Transistor Active Layer Structure for Low Leakage
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Solution Overview
Problem
In organic light-emitting display apparatuses, thin film transistors face issues with parasitic capacitance and leakage currents, which affect the resolution, size, and reliability of the displays, especially as they scale to larger sizes and higher resolutions.
Innovation Solution
The implementation of a thin film transistor structure with a silicon active layer and an oxide active layer, where the oxide active layer is positioned between two silicon active layers, and the use of ion impurity doping to enhance conductivity and reduce parasitic capacitance, along with a specific material selection for the oxide active layer including gallium indium zinc oxide and other oxides, to improve electron mobility and reduce leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional thin film transistor structure is used, then the device complexity is low, but parasitic capacitance increases and leakage currents worsen
Solution Approach 1:
The active layer is segmented into multiple distinct layers: a first silicon active layer, a second silicon active layer, and an oxide active layer positioned between them. This segmentation allows each layer to contribute differently to device performance, with the oxide layer providing low-leakage characteristics while silicon layers provide high mobility, thereby reducing parasitic capacitance and leakage currents without excessive complexity
Solution Approach 2:
The transistor employs a composite active layer structure combining silicon-based materials (first and second silicon active layers) with oxide materials (oxide active layer). This composite structure leverages the high electron mobility of silicon while utilizing the oxide layer's low leakage properties, achieving reduced parasitic capacitance and improved reliability through material composition rather than structural complexity
2Manufacturing precision
If the display is scaled to larger sizes and higher resolutions, then the image quality improves, but parasitic capacitance and leakage currents increase
Solution Approach 1:
Different regions of the active layer are assigned different materials with optimized properties: the oxide active layer provides low leakage in regions where current control is critical, while silicon active layers provide high mobility in regions requiring efficient charge transport. This local optimization allows the transistor to maintain low parasitic capacitance and leakage currents even as display resolution increases
Solution Approach 2:
The patent transitions from a conventional single-layer active structure to a multi-layer vertical structure. By adding the oxide active layer between two silicon active layers, the solution addresses parasitic capacitance and leakage issues through vertical stacking rather than horizontal scaling, enabling high-resolution displays to maintain reliability without being constrained by planar geometry
3Reliability
If ion impurity doping is applied, then conductivity increases, but manufacturing complexity increases
Solution Approach 1:
The patent modifies the electrical parameters of the silicon active layers by controlling ion impurity doping concentrations. By adjusting doping levels in the first and second silicon active layers, the conductivity and electron mobility are optimized while maintaining compatibility with standard manufacturing processes. This parameter optimization achieves improved conductivity control without introducing excessive manufacturing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration decreases parasitic capacitance and increases the on-state current while reducing off-state leakage currents, enhancing the display's performance and reliability for larger and higher-resolution organic light-emitting displays.
Implementation Method 1
The oxide active layer may include one or more oxides selected from the group of gallium indium zinc oxide (G-I-Z-O), an oxide of zinc (Zn), indium (In), gallium (Ga), tin (Sn), cadmium (Cd), germanium (Ge), or hafnium (Hf), and a combination thereof
Implementation Method 2
Regions of the first silicon active layer and the second silicon active layer that do not overlap the gate electrode may be doped with N+ or P+ ion impurities
Data Source
AI summary
Provided is a thin film transistor including an active layer including a first silicon active layer, a second silicon active layer, and an oxide active layer in a space between the first silicon active layer and the second silicon active layer, a gate electrode on the active layer with a gate insulating layer disposed therebetween, and a source electrode and a drain electrode with an interlayer insulating layer disposed between the gate electrode and the source and drain electrodes, the source and drain electrodes being in contact with the first silicon active layer and the second silicon active layer, respectively.