Transistor Contact Structure With Implant-Tuned Gate Mask Etch Selectivity
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Solution Overview
Problem
As semiconductor devices, such as FinFETs, undergo miniaturization, challenges arise in reducing gate mask losses during contact opening etching, leading to increased leakage and decreased device performance.
Innovation Solution
An implantation process is performed to modify the upper regions of gate masks and inter-layer dielectric, increasing their etching selectivity, which reduces losses during the self-aligned contact etching process by forming impurity-rich regions with a high concentration of boron or phosphorous, thereby enhancing the etching selectivity and reducing leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional etching processes are used for contact opening, then the etching process can be completed, but gate mask losses increase leading to increased leakage and decreased device performance
Solution Approach 1:
The patent applies local quality by forming an impurity-rich region specifically in the upper portion of the gate mask through ion implantation. This localized modification creates a region with enhanced etching selectivity precisely where it is needed during contact opening etching, without altering the entire gate mask structure. The impurity concentration gradient (higher at upper regions, lower at lower regions) provides differential protection that reduces gate mask losses while maintaining overall device functionality.
Solution Approach 2:
The patent changes the physical-chemical parameters of the gate mask by implanting impurities (such as silicon, carbon, or nitrogen) into the gate mask material. This modification alters the etching characteristics of the gate mask, creating a region with different etch resistance compared to the original material. The parameter change in impurity concentration directly influences the etching selectivity, allowing the gate mask to better withstand the contact opening etching process and reduce material loss.
2Productivity
If minimum feature sizes are reduced to improve integration density, then more components can be integrated into a given area, but additional problems arise including increased difficulty in controlling etching processes
Solution Approach 1:
The patent applies preliminary action by performing ion implantation to create the impurity-rich region in the gate mask before the contact opening etching process. This preparatory modification ensures that when the etching process subsequently occurs at reduced feature sizes, the gate mask already has enhanced selectivity characteristics built-in, making the etching process more controllable and predictable despite the smaller dimensions involved.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The modified etching selectivity reduces gate mask and inter-layer dielectric losses, improving device performance by minimizing leakage between source/drain contacts and gate electrodes.
Implementation Method 1
An implantation process is performed to modify the upper regions of gate masks and inter-layer dielectric, increasing their etching selectivity, which reduces losses during the self-aligned contact etching process by forming impurity-rich regions with a high concentration of boron or phosphorous
Data Source
AI summary
In an embodiment, a device includes: a gate structure on a channel region of a substrate; a gate mask on the gate structure, the gate mask including a first dielectric material and an impurity, a concentration of the impurity in the gate mask decreasing in a direction extending from an upper region of the gate mask to a lower region of the gate mask; a gate spacer on sidewalls of the gate mask and the gate structure, the gate spacer including the first dielectric material and the impurity, a concentration of the impurity in the gate spacer decreasing in a direction extending from an upper region of the gate spacer to a lower region of the gate spacer; and a source/drain region adjoining the gate spacer and the channel region.