Non-Planar FET Source/Drain Isolation to Suppress DIBL Leakage
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Solution Overview
Problem
Existing methods for forming non-planar transistors face challenges in minimizing leakage paths, particularly the drain-induced barrier lowering (DIBL) effect, which can impact transistor performance as dimensions shrink, often requiring trade-offs that compromise overall performance.
Innovation Solution
The method involves forming a dielectric structure in source/drain trenches before growing epitaxial source/drain regions, which eliminates leakage paths and allows for optimized dimensions of these regions, thereby enhancing transistor performance without compromising it.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods are used to form non-planar transistors, then manufacturing process is simpler, but leakage paths increase and transistor performance deteriorates
Solution Approach 1:
A dielectric structure is formed in the source/drain trenches before the epitaxial source/drain regions are grown. This preliminary formation of the dielectric structure creates an isolation barrier that prevents leakage paths from forming during subsequent processing steps, thereby improving transistor performance without complicating the overall manufacturing process
Solution Approach 2:
The dielectric structure acts as an intermediary element between the substrate and the epitaxial source/drain regions. This intermediate dielectric layer isolates the source/drain regions from the substrate, blocking leakage currents while allowing the transistor to maintain its non-planar geometry and performance characteristics
2Productivity
If transistor dimensions are reduced to increase integration density, then more components fit in given area, but leakage paths increase and performance is compromised
Solution Approach 1:
The dielectric structure is selectively formed only in the source/drain trenches where leakage paths occur, rather than throughout the entire transistor structure. This localized application of dielectric material addresses the leakage problem in specific critical areas while maintaining the overall transistor performance and allowing continued scaling for higher integration density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes leakage currents and maintains or improves transistor performance by eliminating the DIBL effect, ensuring better Ion and Ion/Ioff ratios, even as transistor dimensions decrease.
Implementation Method 1
a dielectric structure...electrically isolated from the substrate by the dielectric structure
Implementation Method 2
growing epitaxial source/drain regions...growing a source/drain region over the dielectric structure
Data Source
AI summary
A semiconductor device is disclosed. The semiconductor device includes a substrate including a semiconductor material. The semiconductor device includes a conduction channel of a transistor disposed above the substrate. The conduction channel and the substrate include a similar semiconductor material. The semiconductor device includes a source/drain region extending from an end of the conduction channel. The semiconductor device includes a dielectric structure. The source/drain region is electrically coupled to the conduction channel and electrically isolated from the substrate by the dielectric structure.