Nanostructured Channel Stack With Vertical Equipotential Region
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Solution Overview
Problem
The scaling down of semiconductor devices increases complexity and leads to variations in dimensions and electrical potential distribution across nanostructured horizontal channel regions, resulting in variations in device parameters such as threshold voltage, drain induced barrier lowering, and current density, affecting intra-device and inter-device variability.
Innovation Solution
Incorporating a nanostructured vertical channel region within a stack of nanostructured horizontal channel regions, surrounded by a gate-all-around structure, to ensure equal electrical potential distribution across the horizontal channel regions, thereby mitigating dimension-related variations and improving current density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are scaled down to increase storage capacity and processing speed, then device performance improves, but manufacturing complexity increases and dimension variations occur
Solution Approach 1:
The channel region is segmented into multiple horizontal channel regions stacked vertically, with each region having controlled thickness. This segmentation allows independent control of electrical potential in each region while maintaining overall device performance, resolving the contradiction between scaling down for higher productivity and managing manufacturing complexity
Solution Approach 2:
The patent transitions from planar 2D channel structures to 3D vertically-stacked channel regions. By adding the vertical dimension, the device achieves higher storage capacity and processing speed without proportionally increasing manufacturing complexity, as the vertical stacking can be achieved through controlled deposition processes
2Quantity of substance
If horizontal channel regions are stacked vertically to increase capacity, then storage capacity improves, but electrical potential distribution becomes non-uniform
Solution Approach 1:
The patent applies equipotentiality by controlling the thickness of each horizontal channel region and their spacing, ensuring that electrical potential is uniformly distributed across all stacked regions. This prevents non-uniform potential distribution that would otherwise occur in vertically-stacked structures, maintaining manufacturing precision while increasing storage capacity
Solution Approach 2:
The patent changes physical parameters including channel region thickness (5-20 nm), spacing between regions, and material composition to achieve uniform electrical potential distribution. By carefully controlling these parameters, the patent resolves the contradiction between increased storage capacity from vertical stacking and uniformity of electrical potential distribution
3Speed
If channel dimensions are reduced to improve performance, then processing speed improves, but parameter variability increases
Solution Approach 1:
The channel is divided into multiple thin horizontal regions (5-20 nm each) stacked vertically. This segmentation reduces the effective channel thickness while distributing the conduction path across multiple regions, improving processing speed while reducing parameter variability through statistical averaging across regions
Solution Approach 2:
The patent uses composite material structures with different materials for channel regions, barriers, and spacers. This allows optimization of each layer's properties to maintain uniform electrical characteristics across the stacked structure, reducing parameter variability while maintaining high processing speed
Data Source
AI summary
A semiconductor device with different configurations of nanostructured channel regions and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a fin structure disposed on a substrate, a stack of nanostructured horizontal channel (NHC) regions disposed on the fin structure, a nanostructured vertical channel (NVC) region disposed within the stack of NHC regions, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the NHC regions and on portions of the NVC region that are not covered by the NHC regions and the fin structure.