Floating CMOS Level Shifter for High dV/dt GaN DC-DC Converters

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Solution Overview

Problem

Designing a floating level shifter for high-voltage, high-frequency GaN-based DC-DC voltage converters is challenging due to incompatibility with low-voltage CMOS processes, high dV/dt triggering false triggers, and the need for special devices or passive components that result in large area and high leakage issues.

Innovation Solution

An all-digital floating level shifter using low-voltage CMOS devices without special devices or passives, which senses and clips the inductor switching node voltage to generate two switching signals acting as ground rails for sublevel shifters, enabling multiplexing and blocking high dV/dt transients, thus eliminating coupling currents and false triggers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If special devices or passive components are used in the floating level shifter, then high-voltage and high-frequency operation is achieved, but device area increases and leakage current increases

Engineering Contradiction:
Improvehigh-voltage capabilityVSAvoiddevice area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The floating level shifter is divided into multiple CMOS transistors connected in series (stacked configuration), where each transistor handles a portion of the total voltage. This segmentation allows the use of standard low-voltage CMOS devices to achieve high-voltage operation without requiring special high-voltage devices, thereby reducing device area and leakage current.

Inventive Principle:
Principle #1Segmentation

2Reliability

If special devices or passive components are used in the floating level shifter, then high-voltage and high-frequency operation is achieved, but leakage current increases

Engineering Contradiction:
Improvehigh-voltage capabilityVSAvoidleakage current
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

By segmenting the voltage handling across multiple standard CMOS transistors in series, each transistor operates within its safe voltage limits and exhibits lower individual leakage current compared to a single special high-voltage device. The stacked configuration reduces total leakage current.

Inventive Principle:
Principle #1Segmentation

3Speed

If the floating level shifter is designed for high-frequency operation, then switching speed is improved, but susceptibility to false triggers from high dV/dt increases

Engineering Contradiction:
Improveswitching speedVSAvoidfalse trigger susceptibility
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent implements a bootstrap circuit that pre-charges the gate of the high-side transistor before switching operations. This beforehand cushioning establishes a stable voltage reference and reduces the impact of high dV/dt transients, preventing false triggers while maintaining high-frequency switching capability.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The bootstrap capacitor acts as an intermediary element that isolates the control circuit from the high dV/dt switching node. It provides a stable voltage reference during switching transitions, mediating between the high-frequency switching operations and the control logic to prevent false triggers.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Area of stationary object

If standard low-voltage CMOS devices are used without special devices, then device area is reduced and leakage is lowered, but high-voltage operation becomes incompatible

Engineering Contradiction:
Improvedevice areaVSAvoidhigh-voltage compatibility
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent uses multiple standard low-voltage CMOS transistors connected in series to handle high voltage. Each transistor only experiences a fraction of the total voltage, making it compatible with standard CMOS process voltages. This segmentation enables high-voltage operation using area-efficient standard devices.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the voltage distribution parameters by introducing intermediate voltage nodes through the stacked transistor configuration. Each transistor operates at a reduced voltage parameter that is compatible with standard CMOS, while the overall system handles high voltage through the series connection.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP4468605A1Floating level shifter for DC-DC converter
Publication Date: 2024.11.27 INTEL CORP
  • EP4468605A1 patent drawingFigure 1
  • EP4468605A1 patent drawingFigure 2
  • EP4468605A1 patent drawingFigure 3~4

AI summary

Embodiments herein relate to a voltage converter with a floating level shifter. The floating level shifter is implemented on a silicon substrate using complementary metal-oxide semiconductor (CMOS) technology while the power train is implemented on a Gallium Nitride substrate. The floating level shifter may be all-digital and avoid the use of passive devices. The floating level shifter is responsive to a voltage output from a bootstrap circuit, a voltage of a switching node of a power train and a drive voltage of the bootstrap circuit, to shift an input signal to an output signal in a charge phase of a switching cycle. The output signal drives a high-side driver for a high-side transistor of the power train, where the voltage output from the bootstrap circuit and the voltage of the switching node alternate in charge and discharge phases of the switching cycle.