Local Interconnect Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
As semiconductor integrated circuits scale down, the increasing complexity and density of devices lead to challenges in reducing parasitic capacitances in interconnect structures, which affect device performance by causing signal integrity issues.
Innovation Solution
The implementation of a local interconnect structure that routes connections directly to the gate, drain, and source terminals of transistor devices, such as finFETs, double-gate devices, and tri-gate devices, to minimize the length of interconnects and thereby reduce parasitic capacitances at the interconnect level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If interconnect length is increased to connect more devices, then device density increases, but parasitic capacitance increases causing signal integrity issues
Solution Approach 1:
The patent divides the interconnect structure into multiple segments including local interconnect structures and global interconnect structures. Local interconnect structures connect nearby devices with shorter lengths, while global interconnect structures handle longer-distance connections. This segmentation reduces the parasitic capacitance of individual interconnect segments while maintaining high device density through efficient routing architecture.
Solution Approach 2:
The patent utilizes multiple interconnect layers stacked in the vertical dimension to route signals between devices. By distributing interconnects across different layers (e.g., M0, M1, M2 layers), the design reduces parasitic capacitance between adjacent conductors by increasing vertical separation while maintaining planar density through multi-layer routing.
2Object-generated harmful factors
If interconnect length is decreased to reduce parasitic capacitance, then signal integrity improves, but device density decreases
Solution Approach 1:
The patent divides the interconnect structure into multiple segments including local interconnect structures and global interconnect structures. Local interconnect structures connect nearby devices with shorter lengths, while global interconnect structures handle longer-distance connections. This segmentation reduces the parasitic capacitance of individual interconnect segments while maintaining high device density through efficient routing architecture.
Solution Approach 2:
The patent utilizes multiple interconnect layers stacked in the vertical dimension to route signals between devices. By distributing interconnects across different layers (e.g., M0, M1, M2 layers), the design reduces parasitic capacitance between adjacent conductors by increasing vertical separation while maintaining planar density through multi-layer routing.
3Quantity of substance
If more interconnect structures are added to connect increased device density, then device complexity increases, but signal integrity deteriorates due to increased parasitic effects
Solution Approach 1:
The patent divides the interconnect structure into multiple segments including local interconnect structures and global interconnect structures. Local interconnect structures connect nearby devices with shorter lengths, while global interconnect structures handle longer-distance connections. This segmentation reduces the parasitic capacitance of individual interconnect segments while maintaining high device density through efficient routing architecture.
Solution Approach 2:
The patent utilizes multiple interconnect layers stacked in the vertical dimension to route signals between devices. By distributing interconnects across different layers (e.g., M0, M1, M2 layers), the design reduces parasitic capacitance between adjacent conductors by increasing vertical separation while maintaining planar density through multi-layer routing.
Data Source
AI summary
The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.