Dielectric Stressor Structure for GAA Channel Mobility
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Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, affecting production efficiency and cost.
Innovation Solution
The process involves forming a semiconductor device structure with finFET and gate all around (GAA) transistor structures using double-patterning or multi-patterning processes, including the formation of sacrificial layers, spacers, and dielectric stressor structures to pattern fins and transistors, and subsequent etching and annealing to create semiconductor nanostructures and metal gate stacks, which improves device performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency and cost are improved, but fabrication process complexity and difficulty increase
Solution Approach 1:
The fabrication process is divided into multiple discrete stages including forming sacrificial layers, depositing spacers, performing double-patterning, and selective etching. Each stage accomplishes a specific function, breaking down the complex task of creating miniaturized devices into manageable sequential steps that can be executed with existing process tools
Solution Approach 2:
Sacrificial layers are formed in advance before the actual transistor structures are created. These preliminary sacrificial structures guide subsequent spacer formation and pattern transfer processes, enabling precise positioning of fins and GAA nanowires without requiring direct patterning at the final feature size
2Area of stationary object
If feature sizes continue to decrease to increase functional density, then chip area utilization is improved, but manufacturing reliability deteriorates
Solution Approach 1:
Dielectric stressor structures are introduced as intermediary elements between the transistor channels and the substrate. These stressor structures apply mechanical stress to the channel region to enhance carrier mobility without requiring changes to the fundamental device geometry, thereby maintaining manufacturing reliability while improving electrical performance
Solution Approach 2:
The patent modifies material parameters by using different dielectric materials with varying stress characteristics and elastic moduli. By selecting appropriate dielectric materials for the stressor structures, the desired level of mechanical stress is achieved to optimize carrier mobility without compromising device reliability
3Manufacturing precision
If double-patterning or multi-patterning processes are used to form fins and transistors, then device performance is improved, but process complexity increases
Solution Approach 1:
The double-patterning process embeds one pattern within another by forming spacers around sacrificial structures, then removing the sacrificial layers. This nested approach allows two complete transistor generations to be formed in sequence, with the second generation nested within the pattern definition of the first, achieving high precision without requiring entirely separate patterning systems
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the production efficiency and reliability of semiconductor devices by improving carrier mobility and reducing parasitic capacitance, leading to better device performance and operational speed.
Implementation Method 1
a dielectric stressor structure between the gate stack and the substrate. The dielectric stressor structure may induce epitaxial structures beside the channel structure to apply stress (e.g., compressive stress) to the channel structure
Implementation Method 2
A thermal operation may be used to anneal the dielectric stressor structure
Data Source
AI summary
A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes multiple semiconductor nanostructures over a substrate and two epitaxial structures over the substrate. Each of the semiconductor nanostructures is between the epitaxial structures. The semiconductor device structure also includes a gate stack wrapped around the semiconductor nanostructures, and the gate stack has a gate dielectric layer and a gate electrode. The semiconductor device structure further includes a dielectric stressor structure between the gate stack and the substrate. The gate dielectric layer extends along and beyond first opposite sidewalls of the dielectric stressor structure.