Buried Contact Plug Formation in Semiconductor Devices
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The formation of contact plugs in buried channel array transistors (BCATs) is challenging due to the difficulty in patterning and the increased complexity, leading to reduced production efficiency and higher manufacturing costs compared to recess channel array transistors (RCATs).
Innovation Solution
A method involving the formation of direct contact plugs through a first interlayer dielectric layer, followed by the creation of bit line structures and barrier patterns, which are used as an etching mask to form buried contact holes and plugs, allowing for self-aligned and efficient contact formation between word lines and source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a protruded gate electrode structure is used in RCAT, then transistor size is reduced and short channel effect is improved, but subsequent contact plug formation and planarization processes become difficult
Solution Approach 1:
The patent inverts the conventional approach by burying the gate electrode below the semiconductor substrate surface instead of protruding it. This is achieved by forming a trench, depositing gate material, and then filling and planarizing the trench, so the gate electrode ends up at a lower level than the substrate top surface, eliminating interference with subsequent contact formation processes
Solution Approach 2:
The gate electrode is formed in advance within a trench structure before the contact plug formation process. By pre-forming the gate electrode at a lower level and planarizing the surface, the substrate is prepared in advance to accommodate subsequent contact holes without the gate protruding into the contact formation area
2Ease of manufacture
If a buried gate electrode structure is used in BCAT to address protrusion issues, then contact formation becomes possible, but patterning difficulty increases and production efficiency decreases
Solution Approach 1:
The patent combines multiple functions into the gate electrode structure: the gate electrode serves both as the control element for the transistor and as a reference structure for forming the contact holes. The contact holes are formed using the gate electrode and previously formed contact plugs as alignment references, merging the gating function with the alignment reference function
Solution Approach 2:
The previously formed direct contact plugs and bit line structures serve as self-aligned references for forming the new contact holes. The etching process uses these existing structures as masks and alignment guides, allowing the contact holes to be automatically positioned correctly without requiring additional complex patterning steps
3Manufacturing precision
If complex patterning processes are used to form contact holes in BCAT, then contact formation is achieved, but manufacturing cost increases
Solution Approach 1:
The existing direct contact plugs, bit line structures, and gate electrode serve as self-aligned references that automatically define the position of the new contact holes. The etching mask is formed by depositing material over these existing structures, which then serve as the alignment reference, eliminating the need for separate complex patterning steps
Solution Approach 2:
The same existing structures (direct contact plugs, bit lines, gate electrode) serve multiple functions: they are the transistor components, the alignment references, and the etching masks. This multi-functionality reduces the number of separate patterning operations needed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the accuracy and efficiency of contact formation in BCATs, reducing the risk of misalignment and improving production yield by forming buried contact plugs that are symmetric about the bit line structures, thereby broadening the contact area and preventing short circuits.
Implementation Method 1
The second and first interlayer dielectric layers are etched using the mask patterns, the barrier patterns and the bit line structures as an etching mask to form buried contact holes
Data Source
AI summary
Methods of forming a contact structure in a semiconductor device include providing a semiconductor substrate including active regions and word lines crossing the active regions. A first interlayer dielectric layer is formed on the semiconductor substrate. Direct contact plugs are formed extending through the first interlayer dielectric layer to contact selected ones of the active regions. Bit line structures are formed on the first interlayer dielectric layer and crossing the word lines that are coupled to the selected ones of the active regions by the direct contact plugs. A second interlayer dielectric layer is formed on the semiconductor substrate including the bit line structures. Barrier patterns are formed extending in parallel with bit line structures and into the second interlayer dielectric layer. Mask patterns are formed overlying an entirety of top surfaces of the direct contact plugs on the second interlayer dielectric layer and the bit line structures. The second and first interlayer dielectric layers are etched using the mask patterns, the barrier patterns and the bit line structures as an etching mask to form buried contact holes and buried contact plugs are formed in the buried contact holes.