Protective Interconnect Layer for Smaller, Aligned Vias
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) are scaled down, the increased density and reduced spacing between conductive features lead to increased capacitance, power consumption, and time delay, posing challenges in manufacturing techniques and device design to maintain performance.
Innovation Solution
A dual damascene process is used with a selective deposition of a protective layer on interconnect dielectric layers to reduce the critical dimension of interconnect vias, preventing damage and misalignment, and maintaining reliability by using a protective layer with a slower etchant removal rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the spacing between conductive features is reduced to increase density, then the element density increases, but the capacitance increases and performance deteriorates
Solution Approach 1:
A protective layer is deposited in advance on the sidewalls of trenches before filling them with conductive material. This preliminary protective coating prevents unwanted material adhesion during subsequent processing steps, enabling tighter spacing between conductive features while maintaining controlled dimensions and reducing parasitic capacitance.
Solution Approach 2:
The protective layer acts as an intermediary between the trench structure and the conductive material. This intermediate layer controls the interface properties, preventing direct contact between the conductive material and trench sidewalls, thereby reducing capacitance while still allowing the trench to serve its confining function.
2Ease of manufacture
If photolithography and mask alignment are used to define feature dimensions, then the manufacturing process is established, but light diffraction and alignment limitations prevent further spacing reduction
Solution Approach 1:
The solution moves from controlling dimensions primarily in the lateral plane through photolithography to controlling dimensions through vertical layer deposition. The protective layer thickness, controlled by atomic layer deposition (ALD), provides precise dimensional control in the vertical dimension, which translates to controlled spacing between conductive features, bypassing photolithography resolution limits.
Solution Approach 2:
The manufacturing approach changes from optical parameter control (photolithography wavelength, numerical aperture) to deposition parameter control (ALD cycle number, precursor flow rates). This parameter change enables sub-lithographic dimensional control, achieving manufacturing precision below the diffraction limit of light while maintaining ease of manufacture through established deposition techniques.
3Loss of energy
If the critical dimension of interconnect vias is reduced to decrease capacitance, then the capacitance and power consumption decrease, but manufacturing precision and alignment become more difficult
Solution Approach 1:
The protective layer serves as a cushioning layer deposited beforehand on the trench sidewalls. This cushioning prevents over-etching or material encroachment that would otherwise compromise via alignment and dimensional control. The layer provides a buffer that maintains precise via dimensions even as critical dimensions are reduced to decrease capacitance and power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the critical dimension of interconnect vias, improves alignment, and decreases capacitance, thereby enhancing the reliability and performance of integrated chips by minimizing the impact of manufacturing limitations.
Implementation Method 1
depositing a protective layer on the first interconnect dielectric layer
Implementation Method 2
performing a third removal process to remove portions of the etch stop layer that are not covered by the first interconnect dielectric layer or the protective layer
Data Source
AI summary
In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes an interconnect dielectric layer over a substrate. An interconnect via is within the interconnect dielectric layer, and an interconnect wire is over the interconnect via and within the interconnect dielectric layer. A protective layer surrounds the interconnect via. The interconnect via vertically extends through the protective layer to below a bottom of the protective layer. The protective layer continuously extends from along an outer sidewall of the interconnect via to along an outer sidewall of the interconnect wire in a first cross-sectional view.