FinFET High-Voltage Isolation Layout for Low-Noise ADC Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in fabricating high voltage devices, such as I/O devices and ADCs, which often remain planar while core devices evolve into multi-gate structures like FinFETs, due to differences in feature sizes and insulation requirements, leading to noise and error issues in ADCs.
Innovation Solution
The method involves forming FinFETs with isolation structures, including an isolation gate structure on a dielectric material within a fin cut trench, using different lithographic processes for core and high voltage device areas to create distinct fin cut trenches and isolation features, allowing for the formation of gate structures with varying lengths to address different voltage requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If planar high voltage devices are replaced with multi-gate high voltage devices, then device performance and integration are improved, but isolation structures are required which take up space and complicate fabrication
Solution Approach 1:
The patent combines the isolation structure with the gate structure by forming the isolation structure within the source/drain recesses and over the channel region, integrating multiple functions into a unified structure that reduces space requirements and fabrication complexity
Solution Approach 2:
The isolation structure is segmented into multiple portions: a first portion within the source/drain recesses and a second portion over the channel region, allowing each segment to serve specific functions and be formed using optimized fabrication processes
2Adaptability or versatility
If different feature sizes are used for core devices and high voltage devices, then operational requirements are met, but fabrication processes cannot be unified
Solution Approach 1:
The patent applies local quality by forming the gate structure with different lengths in different regions: a first gate length for core devices and a second gate length for high voltage devices, allowing each region to be optimized for its specific operational requirements while using the same overall fabrication process flow
Solution Approach 2:
The fin structures are formed with different lengths in different regions before subsequent processing steps, establishing the basis for different device characteristics early in the fabrication process and enabling unified processing of devices with different specifications
3Object-affected harmful factors
If isolation structures are added to multi-gate high voltage devices, then noise and error in ADCs are reduced, but space requirements increase
Solution Approach 1:
The isolation structure is nested within and over the existing device features, with portions placed within source/drain recesses and portions extending over channel regions, maximizing space utilization and reducing the overall device footprint
Data Source
AI summary
Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a substrate having a first area and a second area, a plurality of fin structures extending along a direction over the first area and the second area of the substrate, a first transistor and a second transistor in the first area, a first isolation structure disposed between the first transistor and the second transistor, a first isolation structure disposed between the first transistor and the second transistor, a third transistor and a fourth transistor in the second area, and a second isolation structure disposed between the third transistor and the fourth transistor. The first isolation structure includes a first width along the direction and the second isolation structure includes a second width along the direction. The second width is greater than the first width.