Dual-Layer Source/Drain Structure for CMOS Transistor Control
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Solution Overview
Problem
Existing methods for forming source/drain regions in CMOS transistors using epitaxial processes either result in low activation, high diffusibility layers that are difficult to control, leading to short channel effects, or high activation, low diffusibility layers that increase resistance and form voids under gate spacers.
Innovation Solution
A method involving the formation of a high diffusibility layer and a low diffusibility layer within a recess adjacent to a gate stack, where the high diffusibility layer is annealed to diffuse dopants into the substrate, reducing the need for implantation and minimizing resistance while avoiding void formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single layer of epitaxial silicon with dopant is formed using selective deposition process, then the dopant can easily diffuse out of the layer with low temperature anneal, but diffusion from such layer cannot be well controlled leading to short channel effects
Solution Approach 1:
The source/drain region is divided into multiple layers: a first epitaxial silicon layer with dopant (high diffusibility) and a second epitaxial silicon layer without dopant (low diffusibility). This segmentation allows the first layer to provide dopant diffusion while the second layer controls and limits the diffusion, preventing short channel effects.
Solution Approach 2:
The invention uses a composite structure of two different epitaxial silicon layers with different dopant concentrations and diffusibility characteristics. The combination of a high-diffusibility doped layer and a low-diffusibility undoped layer creates a composite material system that achieves both controlled diffusion and protection against short channel effects.
2Reliability
If a high activation and low diffusibility single layer is formed using cyclical deposition and selective etching, then diffusion is controlled, but resistance within the LDD region increases and voids form underneath spacers
Solution Approach 1:
The source/drain region is segmented into two functional layers: the first layer provides dopant reservoir with high diffusibility for low resistance, while the second layer acts as a diffusion barrier with low diffusibility. This segmentation achieves diffusion control without the need for cyclical processes that cause void formation.
Solution Approach 2:
The second epitaxial silicon layer without dopant acts as an intermediary barrier between the doped first layer and the channel region. This intermediary layer controls dopant diffusion into the channel while allowing adequate dopant presence in the LDD region to maintain low resistance, avoiding the harmful effects of high activation materials.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for controlled dopant diffusion, reducing short channel effects and resistance, and preventing voids under spacers, thereby improving the manufacturing of semiconductor devices.
Implementation Method 1
an annealing process is performed, wherein the annealing process diffuses a first material from the first layer into the channel region
Data Source
AI summary
A system and method for forming semiconductor structures is disclosed. An embodiment comprises forming a high diffusibility layer adjacent to a gate stack and forming a low diffusibility layer adjacent to the high diffusibility layer. After these two layers are formed, an anneal is performed to diffuse dopants from the high diffusibility layer underneath the gate stack to help form a channel region.