Non-volatile Memory Device With Capacitive Selection Lines
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Solution Overview
Problem
Non-volatile memory devices with a multi-layer structure face challenges in selective operation and complex manufacturing processes, limiting their integration density and capacity.
Innovation Solution
A non-volatile memory device is designed with multiple semiconductor layers stacked alternately, each with its own selection line, charge storage layer, and control gate electrode, using epitaxial lateral overgrowth (ELO) for layer formation and selective line patterning, enabling efficient capacitive coupling and increased integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If non-volatile memory devices have a multi-layer structure, then integration density is improved, but selective operation capability deteriorates
Solution Approach 1:
The memory device is divided into multiple independent layers, each with its own selection line (first selection line, second selection line, etc.) and control gate electrode. This segmentation allows each layer to be selectively accessed and operated independently, resolving the contradiction between high integration density and selective operation capability.
Solution Approach 2:
Control gate electrodes are introduced as intermediary elements between the semiconductor layers and charge storage layers. These control gates enable precise control over electron tunneling and charge storage operations in each layer, facilitating selective operation while maintaining multi-layer integration.
2Quantity of substance
If non-volatile memory devices have a multi-layer structure, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is segmented into modular stages: forming semiconductor layers, forming control gate electrodes, forming charge storage layers, and forming selection lines. Each stage can be independently optimized and controlled, reducing overall manufacturing complexity despite the multi-layer structure.
Solution Approach 2:
Control gate electrodes are formed preliminary before the charge storage layers. This preliminary action simplifies subsequent manufacturing steps by establishing the control structure early, which then guides the formation of charge storage layers and selection lines in a more straightforward manner.
3Productivity
If selection lines are capacitively coupled to semiconductor layers, then operational efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
Dielectric layers are introduced as intermediaries between the selection lines and semiconductor layers to establish capacitive coupling. This intermediary approach provides a well-defined manufacturing process with standard dielectric material deposition techniques, reducing precision requirements compared to direct coupling methods.
Solution Approach 2:
The capacitive coupling strength is controlled by adjusting dielectric layer thickness and material properties rather than requiring precise geometric alignment. This parameter-based control simplifies manufacturing by allowing tolerance in positional variations while maintaining consistent electrical coupling characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for increased integration density and simplified manufacturing of non-volatile memory devices, enhancing their data processing capacity and operational efficiency.
Implementation Method 1
at least one first layer selection line capacitively coupled to the at least one first semiconductor layer, and at least one second layer selection line capacitively coupled to the at least one second semiconductor layer
Implementation Method 2
at least one first tunneling storage layer may be between the at least one first semiconductor layer and the at least one first charge storage layer
Data Source
AI summary
A non-volatile memory device and a method of manufacturing the non-volatile memory device are provided. At least one first semiconductor layer and at least one second semiconductor layer are disposed. At least one control gate electrode is disposed between the at least one first semiconductor layer and the at least one second semiconductor layer. At least one first layer selection line is capacitively coupled to the at least one first semiconductor layer. At least one second layer selection line is capacitively coupled to the at least one second semiconductor layer.