Common N-Well Level Shifter Layout to Prevent Latch-Up
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Solution Overview
Problem
Integrated circuits with multiple power domains face challenges in efficiently shifting logical levels between different power supply voltage levels, often leading to latch-up risks and increased space requirements due to separate PMOS transistors operating in separately biased n-wells.
Innovation Solution
A level shifting circuit with a bias circuit that positions PMOS transistors in a common n-well, generating a bias voltage based on the greater of two power supply voltage levels to avoid latch-up risks while reducing space requirements by eliminating the need for separate n-well spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate PMOS transistors are used in separately biased n-wells to shift logical levels between different power domains, then the level shifting function is achieved, but latch-up risks increase and space requirements increase
Solution Approach 1:
The patent merges multiple separately biased n-wells into a single common n-well that serves multiple PMOS transistors operating in different power domains. This consolidation eliminates the need for separate n-well structures, thereby reducing the total area occupied while maintaining proper biasing through a shared well configuration, thus resolving the contradiction between reliability and space requirements
2Reliability
If separate n-wells are used for PMOS transistors in different power domains, then proper biasing is achieved, but device complexity increases
Solution Approach 1:
The common n-well structure serves multiple functions simultaneously: it provides the biasing reference for PMOS transistors operating in different power domains, acts as a shared substrate for multiple devices, and maintains proper electrical isolation. This multi-functional design simplifies the overall device complexity while preserving accurate biasing across different power domains
Data Source
AI summary
A method of manufacturing an IC structure includes forming first through fourth PMOS transistors in an n-well, constructing a bias circuit including the first and second PMOS transistors, constructing a level shifter including the third and fourth PMOS transistors, building a first power distribution structure including electrical connections to each of the first and third PMOS transistors, and building a second power distribution structure including electrical connections to each of the second and fourth PMOS transistors.