Nanosheet Gate Dielectrics With P-Type Dipoles for Multi-Vt Tuning
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Solution Overview
Problem
The challenge in developing nanosheet-based semiconductor devices is the difficulty in implementing p-type dipole materials like aluminum oxide in gate dielectric layers due to solubility issues with conventional hard mask materials, especially in tight processing windows, which hinders the achievement of multiple threshold voltages.
Innovation Solution
The method involves forming a dipole layer over a high-k gate dielectric layer, recessing it to create a processing window, and using thermal treatment to drive the dipole material into the gate dielectric layer, allowing for the patterning and integration of p-type dipoles, enabling the adjustment of threshold voltages in nanosheet-based devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional hard mask materials are used to pattern p-type dipole materials like aluminum oxide, then the patterning process becomes feasible, but the solubility issues cause failure in tight processing windows
Solution Approach 1:
The patent introduces a specialized hard mask material as an intermediary between the p-type dipole material and conventional etching processes. This intermediary material is specifically selected or engineered to be insoluble in the etching chemicals used to pattern aluminum oxide and other p-type dipole materials, thereby enabling successful patterning while maintaining reliability in tight processing windows.
Solution Approach 2:
The patent changes the chemical parameters of the hard mask material to achieve the desired insolubility. By selecting materials with specific chemical compositions or by modifying the hard mask through additional processing steps, the patent alters the solubility parameters to prevent dissolution during the patterning of p-type dipole materials.
2Adaptability or versatility
If multiple threshold voltages are implemented in nanosheet-based devices, then device functionality and performance are improved, but the complex device structures and reduced spacing make it challenging to achieve multiple threshold voltages without penalty to other performance characteristics
Solution Approach 1:
The patent applies local quality by introducing p-type dipole materials at specific locations within the gate dielectric layer of nanosheet-based devices. By selectively placing these dipole materials in certain regions while leaving other regions unchanged, the patent creates devices with different threshold voltages in different areas, thereby achieving multiple threshold voltage offerings without fundamentally altering the overall device structure.
Solution Approach 2:
The patent segments the gate dielectric layer into different functional regions: regions with p-type dipole materials for adjusting threshold voltage and regions without dipole materials for maintaining original performance characteristics. This segmentation allows the device to simultaneously exhibit multiple threshold voltage behaviors while preserving the benefits of the base nanosheet structure.
3Adaptability or versatility
If p-type dipole materials are integrated into gate dielectric layers, then threshold voltage tuning capability is enabled, but solubility issues with conventional hard mask materials hinder the achievement of multiple threshold voltages
Solution Approach 1:
The patent uses a specialized hard mask material as a mediator that enables the integration of p-type dipole materials into gate dielectric layers. This intermediary hard mask material solves the solubility conflict by being chemically inert to the etching processes used to pattern aluminum oxide and other p-type dipole materials, thereby facilitating successful integration while maintaining ease of manufacture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively patterns and integrates p-type dipoles, enabling the tuning of threshold voltages and overcoming the limitations of conventional technologies in achieving multiple threshold voltages in nanosheet-based devices, thereby improving device performance and functionality.
Implementation Method 1
conducting a thermal treatment process to drive the dipole material into the gate dielectric layer
Data Source
AI summary
A semiconductor structure includes a stack of nanostructures, an interfacial layer wrapping around each nanostructure of the stack of nanostructures, a first gate dielectric layer wrapping around the interfacial layer and each nanostructure of the stack of nanostructures, and a gate electrode layer disposed over the first gate dielectric layer. The first gate dielectric layer includes a dipole element. A first concentration of the dipole element at a center line of the first gate dielectric layer is greater than a second concentration of the dipole element at a boundary surface of the first gate dielectric layer interfacing the interfacial layer.