Graphene-Clad Copper Interconnects for Low-Resistance Scaling

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Solution Overview

Problem

The semiconductor industry faces challenges in scaling down metal oxide semiconductor field effect transistors (MOSFETs) and fin field effect transistors (FinFETs) due to increased complexity in manufacturing processes, particularly in depositing graphene films with sufficient adhesion to copper interconnects, which affects resistance and reliability.

Innovation Solution

The use of graphene cladding around copper interconnects in semiconductor devices, either as a cap or encasing multiple sides, to reduce electron scattering and enhance conductivity, while also serving as a diffusion barrier to prevent copper oxidation and corrosion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If metal lines are scaled down to increase storage capacity and processing speed, then device performance improves, but manufacturing complexity increases

Engineering Contradiction:
Improvestorage capacity and processing speedVSAvoidmanufacturing process complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

A graphene cladding layer is introduced as an intermediary between the copper interconnect and the surrounding environment. This single atomic layer serves multiple functions: it reduces electron scattering at the copper surface (improving conductivity), acts as a diffusion barrier to prevent copper oxidation, and provides a template for subsequent manufacturing steps. This intermediary layer enables scaled-down interconnects to maintain reliability despite increased manufacturing complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If graphene film is deposited on copper interconnects to reduce resistance, then conductivity improves, but adhesion becomes insufficient

Engineering Contradiction:
Improveconductivity and resistanceVSAvoidgraphene adhesion to copper
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The graphene cladding is deposited conformally on the copper interconnect surface before subsequent manufacturing steps. This preliminary formation of the graphene layer establishes a stable interface that prevents copper oxidation and maintains low resistance. The conformal deposition ensures uniform coverage, and the resulting structure provides sufficient adhesion for the intended application lifecycle.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Graphene cladding significantly reduces resistance by up to 50% and extends the lifespan of copper metal lines, improving reliability and capacitance, especially at lower metal layers where smaller pitches increase resistance reduction.

Implementation Method 1

graphene cladding around copper interconnects in semiconductor devices, either as a cap or encasing multiple sides, to reduce electron scattering and enhance conductivity

Methodology Applied
Scientific EffectElectron scattering reduction:

Implementation Method 2

serving as a diffusion barrier to prevent copper oxidation and corrosion

Methodology Applied
Scientific EffectDiffusion barrier: Diffusion Barrier

Data Source

PatentUS20230402385A1Graphene-clad metal interconnect
Publication Date: 2023.12.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20230402385A1 patent drawing
  • US20230402385A1 patent drawing
  • US20230402385A1 patent drawing

AI summary

A graphene-clad metal interconnect extends material properties of graphene to both damascene and patterned interconnect structures at lower metal layers, leading to significant reductions in resistance. Graphene cladding can be used with or without a metal barrier/liner. Presence of a barrier/liner can serve to catalyze growth of an overlying graphene layer. Graphene may also be selectively grown on barrier surfaces. Fully integrated structures and process flows for integrated circuits with graphene-clad metallization are described.