Multi-Bridge-Channel FET Layout With Dual-Side Wiring for Dense Logic
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Solution Overview
Problem
The increasing demands for high performance, high speed, and multifunctionality in semiconductor devices have led to challenges in improving the integration density and operating properties of planar metal oxide semiconductor field effect transistors (FETs), prompting the development of FinFETs and gate-all-around-type transistors, but these devices require enhanced electrical properties and reliability.
Innovation Solution
A semiconductor device design featuring fin-shaped active patterns with stacked channel structures and gate structures that surround the semiconductor patterns, along with source/drain patterns and interlayer insulating layers, to improve electrical properties and reliability, and a complex interconnection structure using upper and lower wiring lines and contact vias to form NAND or NOR logic circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If planar metal oxide semiconductor FETs are used to meet increasing demands for high performance and multifunctionality, then integration density can be increased, but operating properties deteriorate due to size reductions
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional FinFET structures with vertical fins extending from the substrate. This dimensional change increases the effective channel area and integration density while maintaining adequate gate control and operating properties through the vertical fin geometry that provides better electrostatic control compared to scaled planar devices.
2Reliability
If FinFETs are developed to overcome limitations in operating properties, then electrical properties improve, but device complexity increases
Solution Approach 1:
The patent employs multiple discrete FinFET devices stacked vertically and interconnected through complex wiring structures. Each FinFET is a separate functional unit with its own gate, source, and drain regions, allowing independent optimization of electrical properties while managing complexity through modular segmentation of the overall device architecture.
Solution Approach 2:
The patent implements vertically stacked FinFET structures where multiple active regions are nested in the vertical dimension. This nesting approach improves electrical properties by providing multiple parallel conduction paths while containing the horizontal footprint, effectively managing device complexity through vertical integration rather than horizontal expansion.
3Reliability
If gate-all-around-type field effect transistors are used to further improve electrical properties, then reliability enhances, but manufacturing complexity increases
Solution Approach 1:
The patent implements gate-all-around structures where the gate electrode completely surrounds the semiconductor fin from all sides, including the top and bottom surfaces. This three-dimensional gate configuration provides superior electrostatic control and enhanced electrical properties compared to planar gates, while the manufacturing complexity is managed through sequential deposition and patterning processes that build the gate structure in multiple stages.
Data Source
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AI summary
A semiconductor device includes: an active pattern (105) extending on a substrate (101) in a first direction (X); first to fourth channel structures stacked, in order, on one region of the active pattern; first and second gate structures respectively crossing the first and second and the third and fourth channel structures, and extending in a second direction (Y); first to fourth source/drain patterns, respectively, connected to both ends of the first to fourth channel structures; a plurality of upper contact vias electrically connecting each of a plurality of upper wiring lines (M1a, M1b, M1C) to at least one of the first to fourth source/drain patterns; a plurality of lower wiring lines (M2a, M2b, M2c) disposed on a lower surface of the substrate (101); and a plurality of lower contact vias penetrating through the substrate and electrically connecting each of the plurality of lower wiring lines to at least one of the first to fourth source/drain patterns.