Backside Contact GAA Structure for Low-Capacitance Current Flow
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Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, leading to issues with processing and manufacturing complexity.
Innovation Solution
The process involves forming FinFET and gate all-around (GAA) transistor structures using photolithography and self-aligned double-patterning or multi-patterning techniques, with sacrificial layers and spacers to create patterns with smaller pitches, and epitaxial growth to achieve desired etching selectivity and oxidation rates, along with the use of dielectric and protection layers to form semiconductor nanostructures and gate stacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency and cost are improved, but fabrication process complexity and difficulty increase
Solution Approach 1:
The fabrication process is divided into multiple discrete stages including forming isolation structures with specific height ratios, sequential deposition of dielectric layers, and staged etching processes. This segmentation allows complex nanoscale fabrication to be broken down into manageable steps that can be controlled and optimized independently.
Solution Approach 2:
Isolation structures are formed in advance with predetermined heights before subsequent device fabrication steps. The dielectric fins are deposited and patterned beforehand to create a structured foundation that guides later self-aligned patterning processes, reducing complexity in real-time fabrication.
2Area of stationary object
If feature sizes continue to decrease to increase functional density, then chip area utilization is improved, but manufacturing reliability deteriorates
Solution Approach 1:
The patent employs precise control of critical parameters including the height ratio of isolation structures (configured to be between 0.5-1.5 times the height of adjacent dielectric fins), deposition thicknesses, and etching depths. These parameter optimizations ensure reliable fabrication at reduced feature sizes while maintaining device performance.
Solution Approach 2:
Dielectric fins and isolation structures serve as intermediary elements that mediate between the substrate and active device regions. These intermediary structures provide mechanical support, electrical isolation, and process alignment references, enabling reliable fabrication of high-density device arrangements.
3Quantity of substance
If complex patterning techniques are used to create smaller pitches, then device density is improved, but process difficulty increases
Solution Approach 1:
Multiple patterning layers are nested within each other through self-aligned processes. The dielectric fins are formed within trenches defined by isolation structures, and subsequent device features are patterned using the fins as alignment references, creating a nested hierarchical structure that simplifies the overall patterning process.
Solution Approach 2:
The patent transitions from two-dimensional planar patterning to three-dimensional structured fabrication by forming vertical dielectric fins and isolation structures with controlled height ratios. This dimensional transition enables higher device density while using simpler in-plane patterning steps, as the density increase is achieved through vertical structure formation rather than complex lateral patterning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of reliable semiconductor devices with improved current flow and reduced parasitic capacitance, enhancing the operation speed and reliability of semiconductor devices by allowing for precise control of layer thickness and structure formation at smaller scales.
Implementation Method 1
epitaxial growth to achieve desired etching selectivity and oxidation rates
Data Source
AI summary
A semiconductor device structure and a formation method are provided. The semiconductor device structure includes a stack of channel structures and includes a first epitaxial structure and a second epitaxial structure adjacent to opposite sides of the channel structures. The semiconductor device structure also includes a gate stack wrapped around each of the channel structures and a backside conductive contact connected to the second epitaxial structure. The second epitaxial structure is between a top of the backside conductive contact and a top of the gate stack. The semiconductor device structure further includes a dielectric fin stacked over an isolation structure. The dielectric fin is adjacent to the second epitaxial structure, and the isolation structure is adjacent to the backside conductive contact. The isolation structure has a first height, the dielectric fin has a second height, and the second height is greater than the first height.