FinFET Gate Isolation Structure to Prevent Bridging Defects

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Solution Overview

Problem

As semiconductor device size shrinks and density increases, there is a risk of short circuits and defects due to residual conductive material bridging adjacent gate electrodes during etching operations, necessitating a process to eliminate bridging across adjacent gate electrodes.

Innovation Solution

The process involves forming insulating layers between adjacent gate electrodes, including an oxidation or nitridation treatment to create a first insulating layer, followed by depositing a second insulating layer, which separates the gate electrodes and prevents electrical bridging, allowing for the formation of high-k gate dielectric and metal gate electrode structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If semiconductor device size is shrunk and density is increased, then device integration is improved, but the risk of short circuits and defects due to residual conductive material bridging adjacent gate electrodes increases

Engineering Contradiction:
Improvedevice integrationVSAvoidshort circuit risk
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

An insulating layer is formed between adjacent gate electrodes before the etching operation that cuts the gate electrodes. This preliminary insulating layer prevents residual conductive material from bridging the gap between adjacent gate electrodes during subsequent etching, thereby eliminating short circuits while allowing continued device miniaturization and density increase

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If gate electrodes are cut by etching operation, then device separation is achieved, but residual conductive material may bridge adjacent gate electrodes causing short circuits

Engineering Contradiction:
Improvegate electrode separationVSAvoidelectrical bridging defect
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

An insulating layer is introduced as an intermediary between adjacent gate electrodes. This insulating layer acts as a mediator that prevents electrical contact between the gate electrodes during etching operations, allowing the gate electrodes to be cut and separated while maintaining electrical isolation through the insulating layer

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly reduces the number of defects and increases device yield by ensuring electrical separation of gate electrodes, even when the opening between them is not properly aligned, thereby enhancing the manufacturing process for semiconductor devices.

Implementation Method 1

an oxidation or nitridation treatment to create a first insulating layer

Methodology Applied
Scientific EffectOxidation: Oxidation

Implementation Method 2

an oxidation or nitridation treatment to create a first insulating layer

Methodology Applied
Scientific EffectNitridation: Nitriding

Implementation Method 3

followed by depositing a second insulating layer

Methodology Applied
Scientific EffectDeposition: Deposition (physical)

Data Source

PatentUS12154962B2Semiconductor device and manufacturing method thereof
Publication Date: 2024.11.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12154962B2 patent drawing
  • US12154962B2 patent drawing
  • US12154962B2 patent drawing

AI summary

A semiconductor device includes plurality of fin structures extending in first direction on semiconductor substrate. Fin structure's lower portion is embedded in first insulating layer. First gate electrode and second gate electrode structures extend in second direction substantially perpendicular to first direction over of fin structures and first insulating layer. The first and second gate electrode structures are spaced apart and extend along line in same direction. First and second insulating sidewall spacers are arranged on opposing sides of first and second gate electrode structures. Each of first and second insulating sidewall spacers contiguously extend along second direction. A second insulating layer is in region between first and second gate electrode structures. The second insulating layer separates first and second gate electrode structures. A third insulating layer is in region between first and second gate electrode structures. The third insulating layer is formed of different material than second insulating layer.