Fin-type MISFET with Dummy Semiconductor Layer for Etching Uniformity
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Solution Overview
Problem
Conventional processes for manufacturing fin-type MISFETs face issues with uniform etching, microloading effects, and gate electrode processability, leading to unsatisfactory transistor properties and reliability.
Innovation Solution
The solution involves forming a semiconductor device with a first semiconductor region having protruding semiconductor layers and a second semiconductor region at both ends, where the second region does not carry channel current, to prevent resist tilting and maintain symmetry during etching, and forming a gate electrode that strides over multiple semiconductor layers to improve uniformity and flatness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single cuboid semiconductor layer is used, then the structure is simple, but the transistor properties and reliability are insufficient
Solution Approach 1:
The invention divides the semiconductor structure into multiple cuboid semiconductor layers (first, second, and third layers) arranged in parallel, transforming a single-layer structure into a multi-layer fin-type structure. This segmentation improves transistor properties by creating multiple channel regions while maintaining manufacturing simplicity through standardized layer formation processes.
2Reliability
If multiple cuboid semiconductor layers are formed, then transistor properties improve, but etching uniformity deteriorates due to microloading effects
Solution Approach 1:
The invention introduces a dummy semiconductor layer (the third layer) at one end to create symmetry in the overall structure. This asymmetric addition actually resolves the symmetry problem by balancing the etching conditions on both sides of the gate electrode, eliminating microloading effects and improving etching uniformity across all semiconductor layers.
Solution Approach 2:
The dummy semiconductor layer is formed in advance during the same etching process as the functional semiconductor layers. By preparing this additional layer beforehand, the invention ensures that the etching process experiences uniform conditions from the start, preventing etching uniformity deterioration before it occurs.
3Ease of manufacture
If semiconductor layers are formed by conventional etching, then the process is straightforward, but resist tilting occurs and symmetry is lost
Solution Approach 1:
By adding a dummy semiconductor layer at one end, the invention creates a symmetric configuration where the first and third layers flank the second functional layer. This symmetric arrangement prevents resist tilting during photolithography and maintains structural symmetry throughout the device, while the overall process remains straightforward as all layers are formed using the same conventional etching steps.
4Manufacturing precision
If the gate electrode strides over multiple semiconductor layers, then uniformity and flatness improve, but the gate electrode structure becomes more complex
Solution Approach 1:
The gate electrode is formed as a single continuous structure that strides over all three semiconductor layers, merging what could have been separate gate electrodes into one unified component. This approach improves uniformity and flatness across the device while avoiding the complexity of forming and aligning multiple separate gate electrodes, as the gate is created in a single formation step.
Data Source
AI summary
A semiconductor device comprising a first semiconductor region and a second semiconductor region,(a) wherein a field effect transistor is comprised of the first semiconductor region comprising at least one semiconductor layer(s) protruding upward from a substrate, a gate electrode(s) formed via an insulating film such that the gate electrode(s) strides over the semiconductor layer(s) and source/drain regions provided in the semiconductor layer(s) on both sides of the gate electrode(s), whereby a channel region is formed in at least both sides of the semiconductor layer(s),(b) wherein the second semiconductor region comprises semiconductor layers protruding upward from the substrate and placed, at least opposing the first semiconductor region at both ends in the direction perpendicular to a channel current direction and the side surface of the semiconductor layers facing the first semiconductor region is parallel to the channel current direction.