Cavity Source/Drain Nanosheet Transistor for Short-Channel Suppression
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Solution Overview
Problem
Current semiconductor devices face challenges in improving element performance and reliability, particularly in scaling and suppressing short channel effects in multi-gate transistors with three-dimensional channels.
Innovation Solution
The semiconductor device incorporates an active pattern with a lower pattern and multiple sheet patterns, featuring a source/drain pattern with an epitaxial region and a cavity region surrounded by semiconductor material, along with a gate structure that includes a gate electrode on the sheet patterns and an inner spacer, which enhances current control and reduces short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistors with three-dimensional channels are used, then device density and current control capability are improved, but short channel effects worsen
Solution Approach 1:
The patent transitions from planar two-dimensional channels to three-dimensional channels with multiple sheet patterns stacked vertically. This dimensional change allows the gate to control the channel from multiple directions (top, bottom, and sides), significantly improving current control capability and suppressing short channel effects while increasing device density without requiring larger gate lengths.
Solution Approach 2:
The channel is divided into multiple discrete sheet patterns (first sheet pattern, second sheet pattern, third sheet pattern) stacked in vertical layers. Each sheet pattern forms an independent conduction path that can be individually controlled by the gate, allowing for better current modulation and reduced short channel effects compared to a single continuous channel.
2Reliability
If gate length is increased to suppress short channel effects, then reliability improves, but device density deteriorates
Solution Approach 1:
Instead of increasing gate length in the planar direction, the patent employs vertical stacking of multiple sheet patterns to enhance gate control. The gate structure extends vertically to contact multiple sheet patterns, providing effective short channel effect suppression while maintaining compact lateral dimensions and high device density.
Solution Approach 2:
The patent changes the geometric parameters of the channel from a single planar layer to multiple vertical layers. By adjusting the number of sheet patterns, their thickness, and spacing, the device achieves improved electrostatic control and reduced short channel effects without compromising density, as the vertical dimension compensates for the maintained small lateral gate length.
3Reliability
If multiple sheet patterns are stacked vertically, then current control capability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent forms all sheet patterns and their associated cavities simultaneously through a single etching process using a unified mask pattern. This preliminary action approach allows multiple complex three-dimensional structures to be created in one step rather than requiring sequential formation of each sheet pattern, significantly reducing manufacturing complexity despite the increased structural complexity.
Solution Approach 2:
The device structure employs nested cavities where first cavities and second cavities are formed within the semiconductor layer, creating a hierarchical three-dimensional architecture. This nesting approach allows multiple functional regions to be integrated vertically without requiring separate processing steps for each cavity, simplifying the overall manufacturing process while achieving complex current control characteristics.
Data Source
AI summary
A semiconductor device is provided. The semiconductor comprises an active pattern including a lower pattern and a plurality of sheet patterns that are spaced apart from the lower pattern in a first direction, a source/drain pattern on the lower pattern and in contact with the plurality of sheet patterns, and a gate structure on opposing sides of the source/drain pattern in a second direction different from the first direction, the gate structure including a gate electrode on the plurality of sheet patterns, wherein the source/drain pattern includes an epitaxial region that comprises a semiconductor material and a cavity region that is inside the epitaxial region and that is surrounded by the semiconductor material.