FDSOI Transistor Floating N-Well Layout for Lower Insertion Loss
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor transistors face challenges in reducing parasitic capacitance and insertion loss, particularly in fully depleted silicon-on-insulator (FDSOI) transistors, which affect their performance and efficiency in RF switching circuits.
Innovation Solution
The semiconductor structure incorporates a floating N-type well region with undoped layers and shallow trench isolation (STI) regions to reduce parasitic capacitance by decoupling the N-type well region from the drain-bulk capacitor, thereby minimizing the figure of merit (FOM) and insertion loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional FDSOI transistor structure is used, then device performance is maintained, but parasitic capacitance and insertion loss increase
Solution Approach 1:
The patent extracts and removes the parasitic diode formed between the N-type well region and the substrate by introducing an undoped layer that decouples the N-type well from the substrate. This extraction of the harmful parasitic structure directly reduces parasitic capacitance and insertion loss without significantly complicating the overall device structure.
Solution Approach 2:
The undoped layer acts as an intermediary between the N-type well region and the substrate, preventing the direct formation of the parasitic diode. This intermediate layer isolates the N-type well from the substrate, thereby reducing parasitic capacitance while maintaining the necessary electrical characteristics of the transistor.
2Ease of manufacture
If N-type well region is directly connected to substrate, then manufacturing is simplified, but parasitic capacitance increases
Solution Approach 1:
The patent extracts the harmful parasitic capacitance by removing the direct connection between the N-type well region and the substrate through the undoped layer, while maintaining a relatively simple fabrication process that builds upon conventional FDSOI manufacturing techniques.
3Object-affected harmful factors
If undoped layer is added to decouple N-type well, then parasitic capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The undoped layer serves as an intermediary structure that reduces parasitic capacitance by decoupling the N-type well from the substrate. While this adds a structural element, it integrates seamlessly with existing FDSOI fabrication processes, minimizing the increase in manufacturing complexity.
4Loss of energy
If floating N-type well with undoped layer is used, then insertion loss is reduced, but device area increases
Solution Approach 1:
The patent extracts the parasitic elements causing insertion loss by removing the direct N-type well to substrate connection, using the undoped layer to create electrical isolation. This approach reduces insertion loss while keeping the additional area occupied by the undoped layer minimal compared to the overall device footprint.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate, an N-type well region over the semiconductor substrate, a FDSOI transistor formed over the N-type well region, a first shallow trench isolation (STI) region over the N-type well region, a first N-type doped region over the N-type well region, a second STI region over the semiconductor substrate, a first P-type doped region over the semiconductor substrate, and a first interconnection element over the first P-type doped region. The first P-type doped region is separated from the first N-type doped region by the second STI region. The first interconnection element is configured to connect the first P-type doped region to a ground. No interconnection element is formed over the first N-type doped region so that the first N-type doped region and the N-type well region are floating.