GAA Gate Stack Structure for Ultra-Low Threshold MOSFETs
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down metal oxide semiconductor field effect transistors (MOSFETs) to achieve ultra-low threshold voltages while maintaining manufacturing complexity and cost-effectiveness, particularly in forming gate structures with nanostructured channel regions that require precise control of work function metals and gate stack thicknesses.
Innovation Solution
The development of gate structures for finFETs and gate-all-around (GAA) FETs with Al-based n-type work function metal layers and Al-free p-type work function metal bi-layers, along with selective formation of Si capping layers, allows for the achievement of ultra-low threshold voltages by optimizing the thickness and material composition of gate stack layers, enabling the formation of FETs with different conductivity types on the same substrate with reduced complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the semiconductor industry scales down the dimensions of MOSFETs to achieve higher storage capacity and faster processing, then device performance and storage capacity are improved, but manufacturing process complexity increases
Solution Approach 1:
The gate structure is segmented into multiple functional layers including metal oxide semiconductor layer, high-k dielectric layer, and work function metal layer. This segmentation allows each layer to be optimized independently for its specific function while maintaining overall device performance during scaling
Solution Approach 2:
The patent changes material parameters by transitioning from traditional silicon-oxide-silicon nitride-silicon oxide (SONOS) structures to metal oxide semiconductor high-k dielectric work function metal (MOS-HK-WFM) structures. This parameter change enables continued scaling by providing better electrical characteristics and control at smaller dimensions
2Productivity
If Al-based n-type work function metal layers are used to achieve ultra-low threshold voltages, then device performance is improved, but oxidation resistance becomes a challenge
Solution Approach 1:
An intermediary protective layer is introduced between the Al-based work function metal layer and the environment. This intermediary layer prevents oxidation of the aluminum while maintaining the electrical functionality, thereby preserving both device performance and reliability
Solution Approach 2:
The patent converts the harmful oxidation tendency of aluminum into a beneficial protective oxide layer. By controlled oxidation, a stable aluminum oxide layer is formed that protects the underlying aluminum from further degradation while maintaining the desired electrical characteristics for ultra-low threshold voltage operation
Data Source
AI summary
The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The method includes forming first and second nanostructured channel regions in first and second nanostructured layers, respectively, and forming first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The forming the first and second GAA structures includes selectively forming an Al-based n-type work function metal layer and a Si-based capping layer on the first nanostructured channel regions, depositing a bi-layer of Al-free p-type work function metal layers on the first and second nanostructured channel regions, depositing a fluorine blocking layer on the bi-layer of Al-free p-type work function layers, and depositing a gate metal fill layer on the fluorine blocking layer.