Gate Driver Short Circuit Protection via Pulsed Pulldown
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Solution Overview
Problem
Conventional gate driver circuits fail to safely manage short circuits in power FETs, leading to excessive heat buildup and component damage due to continuous pulldown currents when a short circuit cannot be overcome.
Innovation Solution
A gate driver circuit with a comparator to detect short circuits, pulsing a pulldown current for a predetermined time, and then switching to a lower hold current to prevent overheating and allow safe shutdown of power FETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate driver continuously provides pulldown current to turn OFF the power FET after detecting a short circuit, then the power FET is forced into the OFF state, but the gate driver will eventually burn up due to excessive power causing failure of the driver chip
Solution Approach 1:
The gate driver provides pulldown current in periodic pulses rather than continuously. The circuit includes a pulse counter that limits the number of pulldown pulses, and after a predetermined number of pulses, the driver transitions to providing only hold current. This periodic action allows the driver to attempt FET shutdown while preventing continuous overheating that would cause driver failure.
Solution Approach 2:
The gate driver dynamically changes the current parameter provided to the FET gate based on the shutdown attempt state. Initially, full pulldown current is provided to force the FET OFF. After a predetermined number of pulses, the current parameter is reduced to a lower hold current level. This parameter change prevents excessive power dissipation in the driver while maintaining enough current to keep the FET in a controlled state.
2Speed
If the gate driver immediately generates pulldown current for all power FETs upon detecting a short circuit, then the faulty power FET is quickly turned OFF, but excessive power is dissipated causing the driver circuit to burn up
Solution Approach 1:
Instead of continuously providing pulldown current at high speed, the system uses periodic pulsed action with a limited number of pulses. The pulse counter controls the duration of high-speed pulldown attempts, and after the predetermined number of pulses, the system transitions to a lower-energy hold current mode. This resolves the contradiction by maintaining fast response for the critical initial shutdown attempt while preventing excessive energy loss.
Solution Approach 2:
The system maintains continuous control action through the transition from pulsed pulldown current to continuous hold current. The useful action of keeping the FET in a controlled OFF state continues without interruption, but the method changes from high-power pulsing to low-power continuous holding. This ensures the FET remains safely OFF while minimizing driver power dissipation.
Data Source
AI summary
A gate driver circuit includes a comparator and a gate driver. The comparator is configured to detect a short circuit in a first power field effect transistor (FET). The gate driver is configured to drive a gate of the first power FET by generating a first signal at a first drive current. In response to the comparator detecting a short circuit in the first power FET, the gate driver is further configured to pulse the first signal at a first pulldown current. After the pulse has ended, the gate driver is further configured to drive the gate of the first power FET at a first hold current. The first hold current is less than the first pulldown current.