Epitaxial Buffer Layer for FinFET Source Drain Leakage Reduction

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Solution Overview

Problem

FinFET semiconductor devices formed on bulk semiconductor substrates face challenges with source and drain region punch through leakage and junction leakage due to sharp dopant profiles, which affect the balance of reduced short channel effects and low extension region resistance.

Innovation Solution

The method involves forming undoped epitaxial semiconductor material on the sidewalls and recessed surfaces of fin structures, followed by doping to create source and drain regions, with a buffer layer to reduce junction leakage and achieve a balanced dopant profile, including an extension dopant region with an abrupt concentration gradient.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If higher drive currents are achieved with smaller transistor dimensions, then device miniaturization is improved, but short channel effects increase

Engineering Contradiction:
Improvedrive currentVSAvoidshort channel effects
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements local quality variations in the source and drain regions by using different dopant concentrations at different positions. The lower dopant concentration adjacent to the fin structure reduces junction leakage and mitigates short channel effects, while the higher concentration further away maintains drive current, thus resolving the contradiction between miniaturization benefits and short channel effect suppression.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces source and drain junction leakage while maintaining low extension region resistance and minimizing short channel effects, enhancing the performance of finFET devices.

Implementation Method 1

An undoped epitaxial semiconductor material is formed on the fin structure. A first portion of undoped epitaxial semiconductor material is formed on the sidewall of at least one of a source region portion and a drain region portion of the fin structure.

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Implementation Method 2

A doped epitaxial semiconductor material is formed on the undoped epitaxial semiconductor material. The undoped epitaxial semiconductor material and the doped epitaxial semiconductor material provide a source region and drain region to the semiconductor device

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS10249714B2Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction
Publication Date: 2019.04.02 RENESAS ELECTRONICS CORP
  • US10249714B2 patent drawing
  • US10249714B2 patent drawing
  • US10249714B2 patent drawing

AI summary

A semiconductor device including a gate structure on a channel region portion of a fin structure, and at least one of an epitaxial source region and an epitaxial drain region on a source region portion and a drain region portion of the fin structure. At least one of the epitaxial source region portion and the epitaxial drain region portion include a first concentration doped portion adjacent to the fin structure, and a second concentration doped portion on the first concentration doped portion. The second concentration portion has a greater dopant concentration than the first concentration doped portion. An extension dopant region extending into the channel portion of the fin structure having an abrupt dopant concentration gradient of n-type or p-type dopants of 7 nm per decade or greater.