Double-Gate Transistor Layout for Narrow-Bezel Display Panels
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Solution Overview
Problem
Display panels face challenges in reducing parasitic capacitance and achieving a narrow bezel design due to limitations in transistor design, particularly in the gate driving circuit, which affects the efficiency and compactness of multimedia devices.
Innovation Solution
A transistor with a double-gate structure is implemented, featuring a first electrode, an active layer with a hole pattern, and a second electrode that overlaps the active layer, reducing parasitic capacitance and allowing for a more compact design by increasing electron mobility and reducing the transistor length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional single-gate transistor structure is used, then the device complexity is low, but the parasitic capacitance is high and electron mobility is limited
Solution Approach 1:
The gate electrode is divided into two separate gates (first gate electrode and second gate electrode) positioned at opposite sides of the active layer. This segmentation allows independent control of the channel from both sides, enhancing electron mobility through dual-gate modulation while managing parasitic capacitance through optimized gate positioning and dimensions
Solution Approach 2:
The transistor structure transitions from a planar single-gate configuration to a three-dimensional double-gate structure where gates are positioned vertically above and below the active layer. This dimensional change enables better electrostatic control and reduced parasitic capacitance by distributing the gate control across multiple spatial dimensions
2Length of moving object
If the transistor length is reduced to achieve compact design, then the display panel bezel can be narrower, but the parasitic capacitance increases
Solution Approach 1:
The channel length is segmented into two independently controlled regions by the first and second gates. This allows the physical transistor length to be reduced for compact design while the effective channel control is maintained through dual-gate modulation, preventing excessive parasitic capacitance accumulation
Solution Approach 2:
The parasitic capacitance is controlled by optimizing parameters including gate electrode dimensions, gate-to-source/drain spacing, and dielectric layer thickness. These parameter adjustments enable reduced transistor length while maintaining acceptable parasitic capacitance levels through precise geometric and material property control
3Reliability
If the overlap area between gate electrode and active layer is increased to improve control, then the electron mobility is enhanced, but the parasitic capacitance increases
Solution Approach 1:
The gate control is segmented into two separate overlapping regions (first gate with active layer, second gate with active layer) positioned at opposite sides. This segmentation allows the total overlap area to be distributed, enhancing electron mobility through dual-side control while reducing parasitic capacitance by avoiding concentrated large-area overlap
Solution Approach 2:
Different regions of the active layer are subjected to different gate control qualities - the regions under the first gate and second gate experience enhanced electric field control improving electron mobility, while the local overlap areas are optimized to minimize parasitic capacitance through controlled dimensions and spacing
Data Source
AI summary
Provided is a transistor including a first electrode, an active layer disposed under the first electrode and having a hole pattern with at least one hole in the source region, a drain region, and an active region overlapping the first electrode, and a second electrode disposed under the active layer. At least one of the first electrode and the second electrode overlaps the hole pattern. This way, the area of the transistor may be reduced, thereby achieving a display panel having a narrow bezel and reducing parasitic capacitance.