Trench Isolation for High-Voltage CMOS Switches
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Solution Overview
Problem
Field-effect transistors fabricated on bulk wafers exhibit poor linearity and intermodulation properties due to non-linear electric fields, and lack electrical isolation, which affects the performance of high-voltage switches in CMOS circuitry used in mobile communication devices.
Innovation Solution
A structure comprising a first well, a second well, and trench isolation regions is formed in a substrate, with the second well having an opposite conductivity type, surrounded by trench isolation regions, to individually isolate active device regions and enhance electrical isolation, allowing for improved high-voltage switching capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If field-effect transistors are fabricated on bulk wafers, then manufacturing cost is reduced, but electrical isolation and linearity deteriorate
Solution Approach 1:
The patent divides the substrate into isolated active device regions using trench isolation structures. These trenches physically segment the bulk substrate, creating electrically isolated regions that prevent non-linear electric field interactions while maintaining the cost advantage of bulk wafer fabrication.
Solution Approach 2:
The trench isolation regions act as intermediary structures between active device regions. By introducing these dielectric-filled trenches, the patent mediates the electrical interaction between adjacent devices, providing the necessary isolation without requiring expensive SOI wafers.
2Strength
If field-effect transistors are stacked to withstand high voltages, then breakdown voltage is improved, but well-substrate capacitance increases
Solution Approach 1:
The patent extracts the problematic capacitance by removing substrate material in the form of trenches around each active device region. This extraction of substrate material beneath and around the device wells eliminates the capacitive coupling between the wells and the substrate, allowing stacked transistors to achieve high breakdown voltages without excessive capacitance.
Solution Approach 2:
The patent addresses the capacitance issue by transitioning from a two-dimensional planar isolation approach to a three-dimensional trench isolation structure. By extending isolation vertically into the substrate with deep trenches, the patent reduces the capacitive coupling area between wells and substrate while maintaining the high-voltage stacking capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration provides enhanced breakdown voltage and reduced well-substrate capacitance, leading to improved figures of merit for field-effect transistors, enabling effective routing of high-frequency signals and increased operating voltages in mobile communication devices.
Implementation Method 1
the substrate is implanted with ions to form a second well having an opposite conductivity type from the first well
Data Source
AI summary
Structures for switches and methods for forming structures that include a switch. A first well and a section well are arranged in a substrate. Trench isolation regions are arranged in the substrate to define multiple active device regions. Each of the active device regions includes a section of the first well that is surrounded by the trench isolation regions. The second well has an opposite conductivity type from the first well. The active device regions and the trench isolation regions are arranged between the top surface of the substrate and the second well, and the second well is contiguous with the trench isolation regions.