Source/Drain Contact Layout for Gate Isolation in FinFETs
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Solution Overview
Problem
As semiconductor device dimensions decrease, self-aligned contact structures face challenges in maintaining electrical isolation between source/drain contacts and gate electrodes, leading to potential short circuits and increased complexity in manufacturing.
Innovation Solution
A method is developed to form self-aligned source/drain contact layers using a gate cutting process and a separator insulating layer, allowing for precise etching and reduced circuit size, while suppressing the formation of rounded contact layer ends.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If self-aligned contact structures are used to reduce device dimensions, then circuit size is reduced, but electrical isolation between source/drain contacts and gate electrodes deteriorates leading to potential short circuits
Solution Approach 1:
The patent divides the contact structure into multiple segments: source/drain contact regions, gate contact regions, and intermediate regions separated by insulating layers. This segmentation prevents direct electrical connection between source/drain contacts and gate electrodes while maintaining compact layout, thus resolving the contradiction between reduced circuit size and maintained electrical isolation.
Solution Approach 2:
The patent introduces intermediate insulating layers and separator structures as mediators between source/drain contact layers and gate electrodes. These intermediary elements provide electrical isolation while allowing the structure to maintain small dimensions, thus resolving the contradiction between compact size and electrical isolation.
2Productivity
If sidewall spacer thickness is reduced to increase device density, then device density increases, but short circuit between source/drain contact and gate electrodes occurs
Solution Approach 1:
The patent introduces intermediate insulating layers and separator structures as mediators between source/drain contact layers and gate electrodes. These intermediary elements provide electrical isolation while allowing the structure to maintain small dimensions, thus resolving the contradiction between compact size and electrical isolation.
Solution Approach 2:
The patent adds vertical isolation layers between the source/drain contact layers and gate electrodes, creating isolation in the vertical dimension rather than relying solely on horizontal spacer thickness. This dimensional approach allows thin spacers while maintaining electrical isolation through the added vertical insulating barrier.
3Ease of manufacture
If conventional etching processes are used for contact layer formation, then manufacturing process is simple, but rounded shapes form at contact layer ends reducing precision
Solution Approach 1:
The patent forms separator insulating layers and defines etch masks before performing the etching process. These preliminary structures guide the etching to stop precisely at the desired location, preventing rounded shapes from forming at the contact layer ends while maintaining process simplicity.
Solution Approach 2:
The patent replaces reliance on mechanical etching stop with chemically-defined stop layers (CESL and separator insulating layers). The etching process stops at these chemically distinct layers, providing precise shape control without the rounded ends that occur with mechanical stopping methods.
Data Source
AI summary
A semiconductor device includes a fin structure, first and second gate structures, a source/drain region, a source/drain contact layer and a separation layer. The fin structure protrudes from an isolation insulating layer disposed over a substrate and extends in a first direction. The first and second gate structures are formed over the fin structure and extend in a second direction crossing the first direction. The source/drain region is disposed between the first and second gate structures. The interlayer insulating layer is disposed over the fin structure, the first and second gate structures and the source/drain region. The first source/drain contact layer is disposed on the first source/drain region. The separation layer is disposed adjacent to the first source/drain contact layer. Ends of the first and second gate structures and an end of the source drain contact layer are in contact with a same face of the separation layer.