Co-integrated Quantum FET Transistors with Asymmetric Dielectric Spacers
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Solution Overview
Problem
The integration of quantum components and FET transistors on the same substrate is challenging due to alignment issues and parasitic passive elements, particularly in 3D architectures where electronic control circuits and quantum qubits are separated, leading to difficulties in managing connections and integrating attenuators and amplifiers close to the qubits.
Innovation Solution
A quantum device is proposed with a semiconductor-on-insulator substrate featuring buried dielectric layers, where quantum components and FET transistors are co-integrated with distinct lateral dielectric spacers, allowing for proper operation and minimizing access resistances, enabling monolithic and coplanar integration using CMOS technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If quantum components and FET transistors are integrated on the same substrate, then device complexity is reduced and production is simplified, but alignment precision becomes more difficult to achieve
Solution Approach 1:
The patent divides the substrate into distinct regions: a first region for quantum components and a second region for FET transistors. This spatial segmentation allows each region to be optimized independently for its specific function while maintaining overall integration, thereby reducing device complexity without compromising alignment precision through separate processing zones.
Solution Approach 2:
The patent introduces a tunnel barrier as an intermediary element between the quantum component and the FET transistor. This tunnel barrier serves as a mediator that facilitates controlled quantum tunneling while providing electrical isolation, enabling the two different components to coexist on the same substrate without direct interference, thus simplifying integration while maintaining manufacturing precision.
2Object-affected harmful factors
If electronic control circuit is separated from qubits, then parasitic passive elements are reduced, but connection management becomes more difficult
Solution Approach 1:
The patent merges the electronic control circuit (FET transistor) and the quantum component into a single integrated structure on the same substrate. This combination eliminates the need for separate connection management between distant components while maintaining low parasitic elements through direct integration and optimized spacing, thereby resolving both issues simultaneously.
3Loss of energy
If attenuators and amplifiers are integrated close to qubits, then signal loss is reduced, but device complexity increases
Solution Approach 1:
The FET transistor in the patent serves multiple functions: it acts as both the quantum component controller and an integrated amplifier for signal readout. This multi-functionality reduces the need for separate attenuator and amplifier components, thereby reducing signal loss through closer integration while keeping device complexity manageable through functional consolidation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration facilitates the co-integration of quantum components and FET transistors on the same substrate, simplifying production and enhancing the control of electric charges, while minimizing access resistances and capacitive coupling, thus improving the operation of quantum devices.
Implementation Method 1
a tunnel barrier arranged between the quantum component and the FET transistor
Implementation Method 2
first lateral dielectric spacers arranged around the first front gate and covering third portions of the active layer which form first access regions
Data Source
AI summary
Quantum device comprising:a quantum component forming a qubit, formed in an active layer of a substrate and comprising:a confinement region;charge carrier reservoirs;a first front gate covering the confinement region;first lateral spacers arranged around the first gate and covering access regions;an FET transistor formed in the active layer, comprising channel, source and drain regions formed in the active layer, a second front gate covering the channel region, and second lateral spacers arranged around the second front gate and covering source and drain extension regions;and wherein a width of the first lateral spacers is greater than that of the second lateral spacers.