MOSFET Source/Drain Buffer Layer for Scaled Device Reliability
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Solution Overview
Problem
The scaling down of metal-oxide-semiconductor field-effect transistors (MOSFETs) in semiconductor devices leads to deterioration in operational properties, necessitating improved electrical and reliability characteristics.
Innovation Solution
The semiconductor device incorporates a substrate with p-type and n-type MOSFET regions, featuring specific active and channel patterns, source/drain patterns with silicon-germanium buffer layers, and a gate electrode structure that includes inner and outer electrodes with spacers, enhancing the device's performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOSFETs are scaled down to meet increasing demand for small pattern size, then device size is reduced, but operational properties deteriorate
Solution Approach 1:
The patent applies local quality by forming a buffer layer with specific material composition (silicon germanium with 5-20 at% germanium) and specific thickness (5-20 nm) only in the source/drain region adjacent to the channel. This localized structural modification improves carrier injection efficiency at the critical source/channel interface without requiring overall device scaling reversal, thereby maintaining operational properties while enabling continued device miniaturization.
Solution Approach 2:
The patent changes material parameters by introducing silicon germanium buffer layer with controlled germanium concentration (5-20 at%) and thickness (5-20 nm) in the source/drain region. This parameter modification creates a gradual band alignment that enhances carrier injection efficiency, allowing the device to maintain performance characteristics during scaling down.
2Reliability
If buffer layer with high germanium concentration is used to improve carrier injection, then electrical characteristics improve, but process failures occur
Solution Approach 1:
The patent optimizes the germanium concentration parameter to a specific range (5-20 at%) and buffer layer thickness (5-20 nm). This parameter optimization achieves the dual benefit of improving carrier injection efficiency (electrical characteristics) while maintaining process stability and preventing manufacturing failures. The controlled parameter range ensures both performance improvement and manufacturing reliability.
Data Source
AI summary
A semiconductor device includes a substrate including a p-type metal-oxide-semiconductor (MOS) field-effect transistor (FET) (PMOSFET) region and an n-type MOSFET (NMOSFET) region, a first active pattern on the PMOSFET region, a second active pattern on the NMOSFET region, a first channel pattern and a first source/drain pattern on the first active pattern, the first channel pattern connected to the first source/drain pattern, a second channel pattern and a second source/drain pattern provided on the second active pattern, the second channel pattern connected to the second source/drain pattern, and a gate electrode on the first channel pattern and the second channel pattern.