Stacked CMOS Image Sensor Voltage Isolation for High Full Well Capacity
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Solution Overview
Problem
The challenge in scaling down CMOS image sensors to achieve lower fabrication costs, higher integration density, and better performance is hindered by the degradation of full well capacity (FWC) due to smaller pixel sizes, which is exacerbated by increased voltages that affect transistor reliability and power consumption.
Innovation Solution
A stacked CMOS image sensor design where a first IC chip with a pinned photodiode and a second IC chip with additional transistors are electrically isolated and biased with different voltages, allowing the pinned photodiode to operate at a higher voltage without increasing the voltage of the transistors, thus maintaining reliability and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If pixel size is reduced to increase integration density, then device size and cost are improved, but full well capacity degrades
Solution Approach 1:
The patent separates the pixel sensor and transistor circuit into different IC chips stacked vertically. The pixel sensor operates at a higher voltage potential on the first IC chip, while the transistor circuits operate at a lower voltage potential on the second IC chip. This vertical dimensional separation allows the small pixel to achieve high full well capacity through elevated voltage without subjecting the transistors to high voltage stress, thus resolving the contradiction between small pixel size and high full well capacity.
Solution Approach 2:
The patent divides the image sensor system into two separate IC chips: the first IC chip contains the pixel sensor, and the second IC chip contains the transistor circuits. This segmentation allows independent optimization of each component - the pixel can be designed for high voltage operation to maximize full well capacity, while the transistors can be designed for low voltage operation to ensure reliability, thereby resolving the contradiction between full well capacity and transistor reliability.
2Quantity of substance
If voltage is increased to enhance full well capacity, then full well capacity is improved, but transistor reliability and power consumption worsen
Solution Approach 1:
The patent introduces a vertical voltage dimension by stacking two IC chips at different voltage potentials. The pixel sensor on the first IC chip operates at a higher voltage (e.g., 3.3V or 5V) to achieve high full well capacity, while the transistor circuits on the second IC chip operate at a lower voltage (e.g., 1.8V or 1.2V) to maintain reliability. This dimensional separation in voltage space allows both high full well capacity and high transistor reliability to coexist.
Solution Approach 2:
The patent segments the system into two voltage domains: a high-voltage domain for the pixel sensor and a low-voltage domain for the transistor circuits. By placing these segments on separate IC chips, the patent enables the pixel to operate at high voltage for maximum full well capacity while the transistors operate at low voltage for optimal reliability, thus resolving the contradiction between full well capacity and transistor reliability.
3Area of moving object
If pixel size is reduced to increase integration density, then device complexity is reduced, but full well capacity and transistor reliability worsen
Solution Approach 1:
The patent moves the transistor circuits from the same plane as the pixel to a vertical dimension by stacking them on a separate IC chip. This allows the pixel to be minimized in area for high integration density while the transistors operate in a separate voltage domain that enables high full well capacity. The vertical stacking also improves heat dissipation and signal integrity, further supporting high performance in small pixels.
Solution Approach 2:
The patent segments the sensor and processing functions into separate IC chips, allowing the pixel to be optimized for minimum area while the transistors are optimized for reliability in a separate low-voltage environment. This segmentation enables small pixel size and high full well capacity to coexist by eliminating the voltage conflict that would otherwise limit full well capacity in small pixels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the full well capacity of the image sensor, enabling high performance even at small sizes without degrading transistor reliability or increasing power consumption, and allows for additional functionality by utilizing unused space on the second IC chip.
Implementation Method 1
The pinned photodiode is configured to accumulate charge in response to incident radiation
Data Source
AI summary
Various embodiments of the present disclosure are directed towards a stacked complementary metal-oxide semiconductor (CMOS) image sensor with a high full well capacity (FWC). A first integrated circuit (IC) chip and a second IC chip are stacked with each other. The first IC chip comprises a first semiconductor substrate, and the second IC chip comprises a second semiconductor substrate. A pixel sensor is in and spans the first and second IC chips. The pixel sensor comprises a transfer transistor and a pinned photodiode adjoining the transfer transistor at the first semiconductor substrate, and further comprises a plurality of additional transistors (e.g., a reset transistor, a source-follower transistor, etc.) at the second semiconductor substrate. A bulk of the first semiconductor substrate and a bulk of the second semiconductor substrate are electrically isolated from each other and are configured to be biased with different voltages (e.g., a negative voltage and ground).