Through Via Insulating Layer for Precise Lower Wiring Etching
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Solution Overview
Problem
Existing semiconductor devices face challenges in ensuring precise etching of lower wiring trenches to maintain reliable connections between through vias and wiring layers, leading to potential defects and reduced reliability.
Innovation Solution
Incorporating a through via insulating layer within a sacrificial layer that serves as an etch stop, preventing excessive etching of lower wiring trenches and ensuring accurate formation of connections between through vias and lower wiring layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the lower wiring trench is etched deeply to connect through vias to the lower wiring layer, then the connection reliability may improve, but the risk of excessive etching increases which can damage the sacrificial layer and reduce manufacturing precision
Solution Approach 1:
The through via insulating layer is formed inside the sacrificial layer before the lower wiring trench etching process. This preliminary action creates a protective barrier that prevents excessive etching, allowing the etching process to proceed deeply enough to ensure connection reliability while stopping before damaging the sacrificial layer, thus maintaining manufacturing precision
Solution Approach 2:
The through via insulating layer acts as an intermediary protective layer between the etching process and the sacrificial layer. It serves as a buffer that absorbs the etching action, preventing direct contact between the etchant and the sacrificial layer, thereby enabling deep etching for reliable connections without compromising the structural integrity of the sacrificial layer
2Manufacturing precision
If the lower wiring trench is etched conservatively to avoid damaging the sacrificial layer, then manufacturing precision may be maintained, but the connection between through vias and lower wiring layer may be unreliable
Solution Approach 1:
By forming the through via insulating layer in advance within the sacrificial layer, the patent enables a conservative etching approach that maintains manufacturing precision while still achieving reliable connections. The pre-formed insulating layer ensures that even with conservative etching depth, the through vias will establish proper connections to the lower wiring layer
3Ease of manufacture
If no protective layer is used during lower wiring trench etching, then the manufacturing process is simpler, but the connection reliability between through vias and lower wiring layer deteriorates due to excessive or insufficient etching
Solution Approach 1:
The through via insulating layer is nested inside the sacrificial layer, creating a multi-layer protective structure. This nested configuration provides reliable connection assurance through controlled etching depth while adding minimal structural complexity, as the insulating layer is contained within the existing sacrificial layer geometry
Solution Approach 2:
The through via insulating layer serves as an intermediary element that mediates between the etching process and the sacrificial layer. This intermediary structure enables reliable connections by controlling etching depth without requiring complex external protective measures, thus maintaining ease of manufacture while improving connection reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of connections between through vias and lower wiring layers by preventing over-etching, thereby improving the overall structural integrity and performance of semiconductor devices.
Implementation Method 1
The through via insulating layer disposed inside the sacrificial layer may serve as an etch stop layer in a process of forming a lower wiring trench in which a lower wiring layer is formed
Data Source
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AI summary
A semiconductor device is provided. The semiconductor device includes: a first substrate; an active pattern extending on the first substrate; a gate electrode extending on the active pattern; a source/drain region on the active pattern; a first interlayer insulating layer on the source/drain region; a sacrificial layer on the first substrate; a lower wiring layer on a lower surface of the sacrificial layer; a through via trench extending to the lower wiring layer by passing through the first interlayer insulating layer and the sacrificial layer in a vertical direction; a through via inside the through via trench and connected to the lower wiring layer; a recess inside the sacrificial layer and protruding from a sidewall of the through via trench in the second horizontal direction; and a through via insulating layer extending along the sidewall of the through via trench and into the recess.