Backside PowerVia Trench Capacitor for High-Density Decoupling
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Solution Overview
Problem
Conventional fill cell capacitance in semiconductor devices achieves low decoupling capacitance density, typically around 20 fF/um2, which is insufficient for effective noise reduction in semiconductor devices.
Innovation Solution
Incorporating a parallel plate trench capacitor between a topside metal layer and a backside metal layer within a fill cell, with an insulating layer comprising alternating ferroelectric and dielectric materials, to increase capacitance density beyond conventional gate-to-source/drain contact area capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional fill cell structure with gate-to-source/drain contact area capacitance is used, then device layout flexibility is maintained, but decoupling capacitance density remains low at approximately 20 fF/um2
Solution Approach 1:
The patent transitions from planar capacitance (gate-to-source/drain contact area) to three-dimensional trench capacitor structure. The trench capacitor extends vertically through multiple metal layers with plates stacked in the vertical dimension, achieving capacitance densities of 60-140 fF/um2 for single trench and 96-244 fF/um2 for dual trenches, representing a 3-5x improvement over conventional approaches.
Solution Approach 2:
The trench capacitor employs composite material structures including alternating layers of conductive plates (aluminum, copper, or tungsten) and dielectric materials (silicon dioxide, silicon nitride, or ferroelectric materials). This composite construction enables high capacitance density while maintaining electrical performance and integration compatibility with standard semiconductor manufacturing processes.
2Quantity of substance
If trench capacitor structure is implemented between topside and backside metal layers, then decoupling capacitance density increases to 60-140 fF/um2, but manufacturing process complexity increases
Solution Approach 1:
The trench capacitor is segmented into discrete components: etched trenches in substrate, deposited dielectric layers, patterned conductive plates, and backside metal layer connections. Each segment can be fabricated using standard semiconductor process modules (etching, CVD, PVD, electroplating), allowing incremental integration into existing manufacturing flows without requiring complete process overhaul.
Solution Approach 2:
The trench capacitor structure serves multiple functions: primary decoupling capacitance provision, noise reduction across frequency ranges, and potential integration with power delivery networks. The same trench structure can accommodate different plate configurations (single or dual trenches, various plate materials) to optimize for different performance requirements while using identical fabrication infrastructure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution significantly enhances decoupling capacitance density, achieving 60-140 fF/um2 for a single trench capacitor and 96-244 fF/um2 for dual trench capacitors, thereby reducing noise in semiconductor devices.
Implementation Method 1
an insulating layer separating the inner plate from the outer plate
Implementation Method 2
an insulating layer comprising alternating ferroelectric and dielectric materials
Implementation Method 3
at least one parallel plate capacitor inside at least one trench between a topside metal layer and a backside metal layer
Data Source
AI summary
A logic cell includes a first trench capacitor disposed between and connecting a topside metal layer to a backside metal layer. The first trench capacitor includes an outer plate, connected to a first power rail on the backside metal layer, an inner plate, connected to a second power rail on backside metal layer, and an insulating layer separating the inner plate from the outer plate.