Gate Isolation Wall With Dielectric Liner for Nanostructure Transistors
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Solution Overview
Problem
The scaling down of semiconductor devices to meet demands for higher storage capacity, faster processing, and lower power consumption introduces challenges such as increased complexity, difficulty in defect control, and issues like threshold voltage variations, metal gate extrusion defects, and electrical shorts due to damaged sidewall spacers and seams or voids in gate isolation structures.
Innovation Solution
The implementation of a gate isolation wall between nanostructure transistors, combined with a dielectric liner and air gaps, to improve threshold voltage uniformity, reduce metal gate extrusion and source/drain epitaxial defects, and prevent electrical shorts by electrically isolating gate structures and using work function metal layers to tune voltage thresholds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate isolation structures are used to electrically isolate gate structures, then electrical shorts are prevented, but seams or voids in the isolation structures cause defects and threshold voltage variations
Solution Approach 1:
A dielectric liner is introduced as an intermediary layer between the gate isolation structure and the channel structure. This liner acts as a mediator that compensates for seams or voids in the gate isolation structure, preventing direct contact between metal gate structures and source/drain contact structures, thereby eliminating electrical shorts while maintaining isolation functionality.
Solution Approach 2:
The dielectric liner is formed in advance before the gate isolation structure is completed. This preliminary cushioning layer is deposited to cover potential defects such as seams or voids that may form during subsequent isolation structure fabrication, ensuring that threshold voltage uniformity is maintained even when isolation structure imperfections occur.
2Productivity
If device dimensions are scaled down to increase storage capacity and processing speed, then device performance is improved, but defect control becomes more difficult and manufacturing complexity increases
Solution Approach 1:
The dielectric liner is formed preliminarily before the gate isolation structure is fully fabricated. This advance preparation ensures that even at scaled dimensions where defect control is difficult, the liner is already in place to compensate for potential seams or voids, maintaining electrical isolation and threshold voltage uniformity without requiring additional complex manufacturing steps.
3Speed
If metal gate structures are used to improve device performance, then processing speed increases, but metal gate extrusion defects occur due to damaged sidewall spacers
Solution Approach 1:
The dielectric liner is formed beforehand to provide protective cushioning during the fabrication of metal gate structures. This preliminary layer prevents direct damage to sidewall spacers and metal gate structures that would otherwise occur during subsequent processing steps, eliminating metal gate extrusion defects while maintaining the high-speed performance benefits of metal gates.
Data Source
AI summary
The present disclosure describes a semiconductor device having an isolation structure. The semiconductor structure includes a set of nanostructures on a substrate, a gate dielectric layer wrapped around the set of nanostructures, a work function metal layer on the gate dielectric layer and around the set of nanostructures, and the isolation structure adjacent to the set of nanostructures and in contact with the work function metal layer. A portion of the work function metal layer is on a top surface of the isolation structure.