CMOS Gate Stack Work Function Tuning With a Single Metal Layer
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Solution Overview
Problem
The existing methods for fabricating CMOS devices with metal gates face increased complexity in achieving both n-type and p-type work functions, leading to difficulties in patterning the gate stack, which complicates the manufacturing process.
Innovation Solution
A method involving the formation of a high-k dielectric layer and a single metal layer with a capping layer, where a portion of the metal layer is treated to change its work function from n-type to p-type using plasma or implantation processes, allowing for the use of a single metal layer to form both n-type and p-type metal gates with similar composition and thickness, simplifying the patterning process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional metal and/or cap layers are used for the gate stack to achieve both N and P work functions, then both N and P work functions can be achieved, but the complexity of the gate stack increases and patterning difficulty increases
Solution Approach 1:
The patent applies parameter changes by treating a single metal layer with plasma or ion implantation to modify its work function. The metal layer is selectively treated in different regions to achieve both n-type and p-type work functions from the same base layer, eliminating the need for multiple metal layers and simplifying the gate stack structure while maintaining the required work function range for both NMOS and PMOS devices
Solution Approach 2:
The patent implements universality by using a single metal layer that serves multiple functions: it provides both n-type and p-type work functions for different device regions. This multi-functional approach allows one layer to replace what would traditionally require separate metal and cap layers, reducing overall gate stack complexity while achieving the same electrical functionality
2Adaptability or versatility
If additional metal and/or cap layers are used for the gate stack to achieve both N and P work functions, then both N and P work functions can be achieved, but patterning difficulty increases
Solution Approach 1:
The patent uses parameter changes through selective plasma or ion implantation treatment of a single metal layer. By controlling the treatment parameters (plasma chemistry, ion energy, dosage) in different spatial regions, the same metal layer achieves different work functions, enabling simplified patterning since only one layer needs to be patterned rather than multiple stacked layers
3Productivity
If scaling down is implemented to increase functional density, then production efficiency increases and costs decrease, but power dissipation increases
Solution Approach 1:
The patent addresses the power dissipation issue arising from scaling by implementing high-k dielectric materials with higher permittivity values. This allows the gate to achieve the same capacitive effect with thinner dielectric layers, enabling better control of scaled transistors and reducing leakage currents that contribute to power dissipation in high-density circuits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the patterning of gate structures for both n-type and p-type MOS devices, making the process more reliable and predictable, while being compatible with current CMOS technology and equipment, reducing manufacturing complexity and costs.
Implementation Method 1
a portion of the metal layer is treated to change its work function from n-type to p-type using plasma or implantation processes
Implementation Method 2
a portion of the metal layer is treated to change its work function from n-type to p-type using plasma or implantation processes
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, an isolation structure in the semiconductor substrate for isolating a first active region and a second active region, a first device formed in the first active region, and a second device formed in the second active region. The first device has a first gate dielectric layer and a first gate electrode over the first gate dielectric layer. The first gate electrode includes at least one of Ta and C, and has a first work function for a first conductivity. The second device has a second gate dielectric layer and a second gate electrode over the second gate dielectric layer. The second gate electrode includes at least one of Ta, C, and Al, and has a second work function for a second conductivity. The second conductivity is different from the first conductivity.