Orthogonal MOS Transistor Implants for Gate-Edge Diode Leakage
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Solution Overview
Problem
In semiconductor fabrication, high-performance CMOS transistors face challenges in reducing gate-edge diode leakage (GDL) while maintaining low mismatch, particularly for low-leakage high-voltage-threshold MOS transistors, as pocket implants used to mitigate short-channel effects tend to increase GDL and mismatch.
Innovation Solution
A two-rotation GDL reduction implant process is implemented, where a pocket implant and a retrograde GDL reduction implant are applied adjacent to the gates of transistors with different orientations, using dopants of opposite conductivity types and specific rotation angles to create counterdoped regions with lower charge carrier densities, thereby reducing GDL without significantly affecting transistor mismatch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pocket implants are used to mitigate short-channel effects, then transistor performance is improved, but gate-edge diode leakage increases
Solution Approach 1:
The implant process is divided into two separate steps: first a pocket implant to mitigate short-channel effects, then a retrograde GDL reduction implant to lower gate-edge diode leakage. This segmentation allows each implant to be optimized independently for its specific function without interfering with the other.
Solution Approach 2:
The retrograde GDL reduction implant uses different parameters than the pocket implant: it employs a higher implantation energy (e.g., 100-200 keV vs. 10-50 keV), a different dopant type (opposite conductivity type), and a shallower peak depth. These parameter changes enable the retrograde implant to reduce GDL without significantly affecting the short-channel effect mitigation achieved by the pocket implant.
2Reliability
If pocket implants are used to mitigate short-channel effects, then transistor performance is improved, but transistor mismatch increases
Solution Approach 1:
By separating the pocket implant and GDL reduction implant into distinct steps with different parameters, the retrograde implant can be optimized to reduce GDL while its shallower peak depth and opposite dopant type minimize its impact on transistor mismatch, thus preserving manufacturing precision.
Solution Approach 2:
The retrograde GDL reduction implant creates a localized doping profile with opposite conductivity type that specifically targets the gate-edge diode region. This localized approach reduces GDL in the critical gate-edge area without significantly affecting the overall transistor channel properties and mismatch characteristics.
3Object-generated harmful factors
If implantation angle is increased to mitigate GDL, then gate-edge diode leakage is reduced, but transistor mismatch increases
Solution Approach 1:
Instead of changing the implantation angle to reduce GDL, the invention changes other parameters: using a retrograde implant with higher energy and opposite dopant type. This alternative parameter set achieves GDL reduction while maintaining a standard implantation angle that does not significantly increase transistor mismatch.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process effectively lowers GDL in MOS transistors while maintaining the same threshold voltage and drive current performance, enhancing the overall leakage reduction and mismatch performance of integrated circuits.
Implementation Method 1
A retrograde gate-edge diode leakage (GDL) reduction implant is implanted adjacent the first and second gates using a second dopant having a second opposite conductivity type
Implementation Method 2
The GDL-reduction implant having a second rotation angle and a second implantation angle
Data Source
AI summary
An integrated circuit is fabricated by forming transistors having gates of orthogonal orientations and implanting, at two first rotations, a first pocket implant using a first dopant type with a masking pattern on a substrate surface layer, the two first rotations respectively forming two first pocket implantation angles and two first pocket implantation beam orientations, and implanting, at two second rotations, a retrograde gate-edge diode leakage (GDL) reduction pocket implant using a second dopant type with the masking pattern on the substrate surface layer, the two second rotations respectively forming two GDL-reduction implantation angles and two GDL-reduction implantation beam orientations. Owing to the different symmetries in implantation angles seen by the two orientations of transistors, leakage is reduced for transistors of both orientations and mismatch is maintained for transistors of one of the orientations, making these transistors suitable for use in analog circuits requiring matched pairs of transistors.