Differential Amplifier Circuit With Common-Mode Attenuation for ECG
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Solution Overview
Problem
Conventional amplifier circuits fail to completely eliminate common-mode signals, leading to saturation issues due to differential-mode signal DC offsets and mismatches between terminals, which limits the amplification of electrocardiogram (ECG) signals.
Innovation Solution
The amplifier circuit design enhances the common-mode rejection ratio (CMRR) by attenuating common-mode input signals within a target frequency band while amplifying differential-mode signals, using a configuration that includes specific transconductance amplifiers, operational amplifiers, and capacitors to manage gains and attenuate DC offsets effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the common-mode signal gain is fixed at unit gain in conventional amplifier circuits, then the circuit structure is simple, but the common-mode signal cannot be completely removed and occupies part of the voltage range causing saturation
Solution Approach 1:
The patent applies dynamics by making the common-mode signal gain adjustable rather than fixed. The common-mode gain can be dynamically changed based on input signal conditions, allowing the amplifier to adaptively optimize common-mode rejection while maintaining circuit functionality. This is achieved through control circuits that adjust the common-mode gain parameter in response to detected signal characteristics.
Solution Approach 2:
The patent implements parameter changes by modifying the common-mode signal gain parameter from a fixed unit gain to a variable parameter that can be adjusted. This allows the system to change the common-mode gain value to optimize performance, preventing saturation by reducing common-mode signal amplitude when necessary while maintaining the ability to reject common-mode interference.
2Productivity
If the differential-mode signal has DC offset, then the amplifier circuit amplifies the signal, but the DC offset causes the amplifier circuit to saturate more easily
Solution Approach 1:
The patent applies taking out by separating the DC offset component from the differential-mode signal through dedicated DC offset processing circuits. These circuits extract and handle the DC offset component independently, preventing it from causing saturation in the main amplification path while preserving the AC signal amplification functionality.
Solution Approach 2:
The patent uses intermediary circuits specifically designed to handle DC offset components. These intermediary processing stages act as mediators between the input signal and the main amplifier, conditioning the signal by removing or managing DC offsets before they can cause saturation, thereby protecting the main amplification path.
3Ease of operation
If there is mismatch between the positive terminal and negative terminal, then the amplifier circuit operates, but the common-mode signal cannot be removed completely requiring back-end subtraction circuit
Solution Approach 1:
The patent applies preliminary action by implementing common-mode signal processing and rejection mechanisms before the signal reaches the output stage. The common-mode gain adjustment and rejection occur in advance within the amplifier circuit itself, eliminating the need for subsequent back-end subtraction circuits and improving overall system efficiency.
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AI summary
The present application discloses an amplifier circuit (100), a chip and an electronic device, which generates a positive output signal (VOP) and a negative output signal (VON) according to a positive input signal (VIP) and a negative input signal (VIN), wherein the positive input signal and the negative input signal have a corresponding input differential-mode voltage and input common-mode voltage, and the positive output signal and the negative output signal have a corresponding output differential-mode voltage and output common-mode voltage, and the amplifier circuit includes: an amplifying unit (120), configured to receive the positive input signal and the negative input signal and generate the positive output signal and the negative output signal; and an attenuation unit (130), including: a positive common-mode capacitor (107) and a negative common-mode capacitor (117), configured to attenuate the input common-mode voltage below a first specific frequency; and a differential-mode capacitor (110), configured to attenuate the input differential-mode voltage below a second specific frequency.