Analog Monitoring Circuit ABIST Using Ramp Signal Time Windows
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Solution Overview
Problem
Existing analog built-in self-test (ABIST) methods for semiconductor devices face challenges in achieving low power consumption, high integration, and high speed, with limited resolution and increased chip area due to the use of multiple clock generating circuits and digital codes for determining normal operation, and slow performance due to reliance on low pass filters.
Innovation Solution
An electronic circuit incorporating a ramp signal generator, oscillator, monitoring circuit, and logic controller that operates in multiple modes to perform ABIST, using ramp signals and comparators to determine normal operation based on transition windows, allowing for efficient power management and high-speed testing with infinite resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple clock generating circuits and digital codes are used to determine normal operation, then measurement precision is improved, but device complexity and chip area increase
Solution Approach 1:
The patent changes the fundamental parameter from digital code-based measurement to ramp signal time-window-based measurement. By using a ramp signal with a predetermined slope and comparing its voltage level at a specific time point against a reference voltage, the system achieves infinite resolution without requiring multiple clock circuits or complex digital codes, thereby resolving the contradiction between measurement precision and device complexity
Solution Approach 2:
The patent extracts and removes the unnecessary clock generating circuits and digital coding components from the ABIST system. By eliminating these complex components and replacing them with a simple ramp signal generator and comparator, the system achieves the same measurement function with significantly reduced chip area and device complexity while maintaining or improving resolution
2Reliability
If low pass filters are used in existing ABIST methods, then noise filtering is improved, but speed performance deteriorates
Solution Approach 1:
The patent substitutes the mechanical/filter-based noise filtering system (low pass filters) with an electronic timing-based measurement system. By using a ramp signal and measuring the voltage level at a precisely controlled time point, the system inherently captures the instantaneous value without requiring filtering, thus achieving both noise immunity and high speed performance simultaneously
3Reliability
If existing ABIST methods are implemented, then analog circuit testing is enabled, but power consumption and integration efficiency worsen
Solution Approach 1:
The patent implements periodic action by using a single-phase clock signal that is periodically enabled only during the ABIST operation. The ramp signal is generated and the measurement is performed only when needed, rather than continuously operating complex circuits. This periodic operation significantly reduces power consumption while maintaining the analog circuit testing capability
Solution Approach 2:
The patent achieves multi-functionality by using a single clock signal and ramp signal generator that can serve both normal circuit operation and ABIST functions. The same comparator and logic controller are used for both monitoring external output voltage and performing self-test, eliminating the need for separate dedicated test circuits and reducing overall power consumption
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enables efficient, high-speed ABIST with low power consumption and high integration, providing infinite resolution and normal/abnormal operation determination, thereby addressing the limitations of existing methods.
Implementation Method 1
a ramp signal generator configured to generate a first ramp signal
Implementation Method 2
a first comparator configured to generate a comparator output
Data Source
AI summary
An electronic circuit includes a ramp signal generator, an oscillator, a monitoring circuit and a logic controller. The ramp signal generator generates a ramp signal. The oscillator generates a clock signal. The monitoring circuit operates in an operation mode selected from a first mode of monitoring an external output voltage and a second mode of performing an analog built-in self-test (ABIST), and generates a comparator output. The logic controller controls the monitoring circuit to operate in the operation mode. When the monitoring circuit operates in the second mode, the logic controller counts the clock signal, controls the monitoring circuit to perform the ABIST based on the ramp signal, and generates an ABIST output indicating whether the monitoring circuit operates normally based on a value of the counting and the comparator output.