Analog Bitscan Erase Control for Memory Cell Endurance
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Solution Overview
Problem
Current non-volatile memory devices face challenges in optimizing erasing operations to improve performance, reliability, and endurance due to limitations in existing erasing techniques, which often result in over-erasing and reduced memory cell endurance.
Innovation Solution
The implementation of an analog bitscan operation that generates multiple output options (strong pass, weak pass, weak fail, and strong fail) allows for dynamic adjustment of erase parameters, such as voltage step sizes, to optimize the erasing process, ensuring precise control and minimizing over-erasing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional erasing techniques are used, then the erasing operation is simple to implement, but over-erasing occurs and memory cell endurance is reduced
Solution Approach 1:
The erasing operation dynamically adjusts the erase pulse voltage based on analog bitscan results. The voltage step size changes from an initial larger step to a smaller refined step when the erase operation approaches completion, preventing over-erasing while adapting to the actual state of memory cells during the process
Solution Approach 2:
An analog bitscan operation provides continuous feedback during the erasing process by generating multiple output options (strong pass, weak pass, weak fail, strong fail). This feedback mechanism allows the system to monitor erase progress and adjust parameters in real-time, ensuring precise control and preventing over-erasing
2Measurement precision
If fixed voltage step sizes are used in erasing, then the erasing process is simple to control, but precision is reduced and over-erasing occurs
Solution Approach 1:
The voltage step size transitions from a fixed initial value to a dynamic adjusted value based on analog bitscan outcomes. When weak fail or strong fail is detected, the system switches to a smaller voltage increment, enabling precise control near the erase completion point while maintaining simple control for the majority of the erasing process
Solution Approach 2:
The erase pulse voltage parameter is changed dynamically during the operation. The system starts with a larger voltage step for rapid erasing and transitions to a smaller voltage step when approaching completion, as determined by analog bitscan results, thereby achieving both efficiency and precision
3Reliability
If multiple voltage steps are applied to ensure complete erasing, then erasing reliability is improved, but the risk of over-erasing increases
Solution Approach 1:
The analog bitscan operation provides continuous feedback during the multi-step erasing process, generating output options (strong pass, weak pass, weak fail, strong fail) that indicate the actual erase status. This feedback allows the system to stop at the appropriate point, ensuring complete erasing without excessive voltage application that would cause over-erasing
Solution Approach 2:
The system applies multiple voltage steps with changing magnitudes - starting with larger steps for efficient erasing and transitioning to smaller steps near completion. This parameter change strategy ensures thorough erasing while minimizing the risk of over-erasing by reducing voltage increment when approaching the target state
Data Source
AI summary
The memory device includes a plurality of memory cells which are arranged in a plurality of word lines. The plurality of word lines includes a selected group of word lines to be erased in an erasing operation. The memory device also includes circuitry that is configured to erase the memory cells of the selected group of word lines in at least one erase loop. The at least one erase loop includes an erase pulse, an erase-verify operation, and an analog bitscan operation. The circuitry is configured to determine an output of the analog bitscan operation, the output being one of at least three options. The circuitry is also configured to set at least one erase parameter based on the output of the analog bitscan operation.