Read-Only Memories TRIZ Cases

A control circuit applies writing voltage to adjacent word lines before programming memory cells.

Segmented page buffers process parallel sensing data to reduce program verify time while maintaining high storage capacity.

Current limiting circuits prevent device failure during SET operations by enforcing maximum current thresholds on reversible resistance-switching memory cells.

Segmenting I/O terminals via a test control unit enables direct memory access, resolving probe test limitations without increasing package area.

Bias voltage acceleration reduces test time while maintaining accurate data loss analysis for resistive switching memory devices.

A memory device staggers sub-block read operations using separate row decoders and voltage switch transistors to manage supply current demands.

A memory controller adjusts read bias sets using modification arrays and accumulated fail bit counts.

A nonvolatile memory device adjusts charge sharing between a selected cell and sensing node based on adjacent word line states.

Adjusts adjacent word-line voltages based on distance from the boundary word-line to optimize read operations.

Segmenting programming passes with dynamic gate voltage reduces time spent on fast cells while preventing over-programming of slow ones.

Dynamic test time and voltage adjustments compensate for bit line resistance variations in nonvolatile memory arrays.

A non-volatile static random access memory uses a backup determination unit to check data states before writing.

Merging four ROM bitcells onto two shared bit lines reduces chip area and power leakage while maintaining data capacity.

Background scheduler rewrites NAND data at temperature-dependent intervals to prevent retention loss beyond ECC correction limits.

A memory control method adjusts read voltage levels using preliminary data reads to optimize decoding operations.

A master device transmits data to a slave device over a shared power line using voltage level changes, while the slave device modulates line load to send feedback signals back.

A nonvolatile memory device performs program and verification operations using a reference voltage to ensure cells reach the required threshold.

A replica source follower circuit dynamically adjusts gate voltage to stabilize memory cell input signals.

A voltage generating unit uses an oscillating unit to create clock signals with staggered timing for serial pump operation.

Multiple memory control units access NAND flash banks through a crossbar switch, resolving sequential transfer rate limitations in mixed workloads.

Segmenting memory blocks into sub-memory units sharing bit lines to enable selective voltage application during erase cycles.

A semiconductor memory device skips verify operations for bad strings using a dedicated register to optimize the erase process.

A complementary antifuse memory cell design selectively stresses one antifuse to store data.

A dedicated extension register manages additional functions via specific commands, resolving host software modification requirements.

Merging repair fuse circuits with storage blocks reduces circuit area while maintaining reliability for failed cell substitution.

Dual sensing latch units perform simultaneous verification operations to reduce programming time while narrowing threshold voltage distribution.

A page buffer outputs a pass signal to set program start voltage for subsequent pages.

Timing circuitry detects specific trigger signals to dump error logs from memory devices, resolving synchronization delays during host link loss.

A nonvolatile memory device uses a ready busy signal to indicate plane status for command execution.

Incorporating inversion indication bits reduces read current by storing inverse data, lowering power consumption in EEPROM arrays.

A weight-based repair algorithm selects defective NAND memory blocks for redundant column substitution to maximize coverage.

A repair circuit uses priority logic to store addresses from failing memory banks.

A cross-point memory recovery method detects threshold voltage drift in selectors during power-up to restore reliable data access.

Dynamic voltage adjustment via analog bitscan prevents over-erasing, extending memory cell endurance while maintaining precise control.

A virtual ground sensing circuit discharges a conductive line to a low capacitance sense node to detect polarization states in ferroelectric memory cells.

Distinct demarcation voltages for verify and read operations eliminate access delays caused by threshold voltage drift in phase change memory.

A program verify control circuit measures source line voltage to skip redundant sensing operations.

A differential fuse-readout circuit uses complementary signals to verify data accuracy and improve reading speed.

A memory circuit detection circuit latches output signals and disrupts the current path between the non-volatile memory cell and the sense amplifier.

A serial-parallel sense scheme reduces flash memory access time by performing two-stage sensing with dynamic reference currents.

Dynamic reference cells track threshold voltage shifts from bit disturb and charge loss, maintaining stable sensing margins in flash memory arrays.

Adaptive body bias adjusts substrate voltage based on error metrics and temperature variations, reducing read errors in NAND flash memory.

Controller assigns location-based likelihood values to outer memory cells, enhancing error correction reliability across the array.

Dynamic bitline voltage control prevents undesired snapback in deselected cells while allowing accurate programming of selected phase change memory cells.

Direct voltage application via a dedicated BE line prevents selection transistor breakdown and reduces chip area.

A semiconductor memory device uses a voltage adjustment circuit to stabilize node voltages during data latching operations.

Segmented programming sequences reduce program disturbance effects on nearest memory cells while maintaining high productivity.

A nonvolatile memory device uses plane select and hold signals to enable or disable planes based on program states.

A writing circuit uses variable gate voltages to control programming verification in non-volatile memory cells.

Dynamic voltage adjustment during post-write verification prevents premature marking of flash storage elements as faulty due to thermal fluctuations.