ROM Architecture Selective Encoding Bit Line Merging
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Solution Overview
Problem
Conventional ROM bitcells and memory arrays face inefficiencies in area usage, cost, and power consumption due to high current leakage, making them unsuitable for applications requiring significant on-chip read-only memory.
Innovation Solution
The implementation of improved ROM bitcells and arrays that store multiple logic states per memory cell using a transistor with program nodes connected to bit lines, allowing for selective encoding and decoding methods based on dominant logic states, reducing power consumption and area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional ROM bitcells are used to store data, then the memory array can be implemented, but the chip area is large and cost is high
Solution Approach 1:
Multiple memory cells are merged to share common bit lines. Specifically, four memory cells share two common bit lines, allowing the same bit lines to be used for reading data from multiple cells by selectively activating different word lines. This merging reduces the total number of bit lines required, thereby reducing chip area while maintaining data storage capacity.
Solution Approach 2:
The common bit lines serve multiple functions: they are shared by multiple memory cells for data reading operations. The same bit lines can be used to read from different memory cells at different times by selecting different word lines, making the bit lines universal resources that increase storage capacity without proportionally increasing area.
2Use of energy by moving object
If conventional ROM bitcells are used, then the memory array can operate, but power consumption is high due to current leakage
Solution Approach 1:
The memory array is segmented into multiple blocks, each with its own set of word lines and shared bit lines. This segmentation allows selective activation of only the necessary memory blocks during read operations, reducing the overall current leakage by keeping other blocks in a low-power state rather than having the entire array active simultaneously.
3Quantity of substance
If more bit lines are added to increase storage capacity, then data storage capacity increases, but chip area and cost increase
Solution Approach 1:
Multiple memory cells are merged to share common bit lines. Specifically, four memory cells share two common bit lines, allowing the same bit lines to be used for reading data from multiple cells by selectively activating different word lines. This merging reduces the total number of bit lines required, thereby reducing chip area while maintaining data storage capacity.
Solution Approach 2:
The patent introduces a hierarchical addressing scheme that adds a block selection dimension. Instead of directly addressing individual cells, the system first selects a block and then addresses cells within that block. This dimensional change allows the same physical bit lines to access multiple logical memory locations across different blocks, effectively increasing storage capacity without adding proportional physical infrastructure.
Data Source
AI summary
Embodiments provide improved memory bitcells, memory arrays, and memory architectures. In an embodiment, a memory array includes a plurality of memory cells to store data bits. Each of the plurality of memory cells includes a transistor having drain, source, and gate terminals, and a plurality of program nodes, each of the program nodes charged to a predetermined voltage and coupled to a respective one of a plurality of bit lines. For each memory cell in a subset of the plurality of memory cells, none of the plurality of program nodes is coupled to the drain terminal of the transistor to program the each memory cell in the subset of the plurality of memory cells to store at least one data bit, the at least one data bit is most occurred between the data bits.