Dynamic Gate Voltage Adjustment for Flash Memory Programming
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Solution Overview
Problem
Flash memory devices face inefficiencies due to manufacturing and material variations, leading to differences in programming rates among memory cells, which can result in over-programming faster cells and prolonging the programming time for entire memory systems.
Innovation Solution
A two-stage programming method is employed, where the initial stage quickly adjusts the threshold voltage, and a second stage fine-tunes it using dynamic gate voltage and bit line biasing to differentiate between fast and slow programming cells, reducing the number of pulses needed to reach the target state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a series of incrementally increasing programming pulses are used to program memory cells to the target threshold voltage, then the memory cells can be reliably programmed to the desired state, but the programming time is prolonged due to the need to program all cells including the faster ones that require fewer pulses
Solution Approach 1:
The patent segments the programming process into multiple passes, where each pass targets a specific subset of memory cells based on their programming speed characteristics. Fast programming cells are identified and programmed in earlier passes, while slow programming cells are targeted in later passes, allowing the system to optimize programming time for each group rather than using a uniform approach for all cells.
Solution Approach 2:
The patent implements dynamic programming pulse voltage adjustment based on the threshold voltage distribution characteristics of the memory array. The programming pulse voltage is dynamically modified between passes to target different portions of the distribution, enabling the system to adapt to the actual programming state and cell performance variations rather than using fixed voltage levels.
2Loss of time
If the programming process is optimized for fast programming cells by reducing the number of pulses, then programming time is reduced, but slow programming cells may not reach the target threshold voltage and over-programming occurs
Solution Approach 1:
The patent applies partial programming action in each pass, where not all memory cells are programmed to the full target threshold voltage in a single pass. Instead, each pass programs cells to an intermediate state, with subsequent passes completing the programming for cells that require additional pulses. This prevents over-programming while ensuring all cells reach the target state.
Solution Approach 2:
The patent incorporates verify operations that provide feedback on the threshold voltage distribution and individual cell states. This feedback information is used to adjust the programming pulse characteristics and determine which cells require additional programming passes, enabling precise control over the programming process and preventing both under-programming and over-programming.
Data Source
AI summary
Methods for programming and memory devices are disclosed. In one such method for programming, a first programming voltage applied to control gates of a group of memory cells generates a maximum threshold voltage of the group of memory cell threshold voltages. A voltage difference between the maximum threshold voltage and a maximum target voltage is used as a gate step voltage for a second programming voltage. Fast and slow programming memory cells are determined from the distribution resulting from the second programming voltage. An effective gate voltage applied to the control gates of the fast programming memory cells is less than an effective gate voltage applied to the control gates of the slow programming memory cells during the third programming voltage.