Serial-Parallel Sense Scheme for Flash Memory Access Time
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Solution Overview
Problem
Conventional flash memory sensing schemes in 90 nm and 65 nm process technology are slow due to the need for multiple level ramping, which increases access time and is susceptible to 1/f noise and Random Telegraph Signal (RTS) noise, making them inefficient for multi-level cell (MLC) data access.
Innovation Solution
A serial-parallel sense scheme that directly ramps the wordline to cell levels L2 and L3, eliminating the need for a third sense operation, and uses dynamic reference currents to differentiate cell states, allowing for faster access and reduced noise by performing sense operations in two stages instead of three.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the wordline ramps through three different levels to sense four possible cell states, then all cell states can be differentiated, but the access time increases and productivity decreases
Solution Approach 1:
The sensing operation is divided into two independent stages: a first sense operation that ramps the wordline to a first cell level to sense a first bit, and a second sense operation that ramps the wordline to a second cell level to sense a second bit. This segmentation allows each stage to complete independently without requiring three sequential ramps, thereby reducing access time while maintaining the ability to differentiate all four cell states.
Solution Approach 2:
The patent employs dynamic reference currents that are adjusted based on the sensed cell state. During the first sense operation, a first reference current is used, and during the second sense operation, a second reference current is applied. This dynamic adjustment of reference currents enables faster convergence and reduces the time required for accurate cell state differentiation.
2Measurement precision
If conventional sensing schemes are used with multiple level ramping, then cell states can be sensed, but 1/f noise and RTS noise increase
Solution Approach 1:
The patent extracts and eliminates the third sense operation from the conventional three-level ramping scheme. By performing sensing in only two stages with appropriately selected reference currents, the patent removes the source of additional noise that would be introduced by a third ramping operation, thereby reducing 1/f noise and RTS noise while maintaining accurate cell state sensing.
Solution Approach 2:
The patent changes the sensing parameters by using different reference currents for different sensing stages. A first reference current is used during the first sense operation and a second reference current during the second sense operation. This parameter change optimizes the signal-to-noise ratio at each stage and reduces the cumulative noise effect compared to conventional uniform reference current schemes.
3Loss of information
If three sense operations are performed, then complete data retrieval is achieved, but the Read Window Budget is reduced
Solution Approach 1:
The patent performs preliminary sensing in the first sense operation by sensing the most significant bit (MSB) using a first reference current. This preliminary action allows the system to determine part of the cell state information earlier, enabling subsequent operations to be optimized or skipped, thereby preserving Read Window Budget while ensuring complete data retrieval through the second sense operation if needed.
Solution Approach 2:
The patent enables skipping the third sense operation by using two-stage sensing with dynamically adjusted reference currents. The first sense operation senses the MSB, and based on this information and the application of a second reference current in the second sense operation, the system can determine the remaining bit without requiring a third ramping operation, thus rushing through the sensing process faster and preserving Read Window Budget.
Data Source
AI summary
A method of sensing data in a multi-level cell memory using two or less sense operations and adjusting column load is provided. A sensing circuit implementing a serial-parallel sense scheme is also provided. The column loads are re-configurable based on the sensing circuit and the serial-parallel sense scheme.