Memory Controller Read Bias Tracking via Accumulated Fail Bit Feedback

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Solution Overview

Problem

Memory systems, particularly NAND-based storage devices, face challenges in maintaining optimal read biases due to varying access frequencies and physical characteristics of memory blocks, leading to changes in read voltage threshold distributions, which affect the reliability and quality of service (QoS).

Innovation Solution

A scheme is implemented to track and adjust the optimal read bias by selecting a read bias set, modifying it using modification arrays, performing read operations, accumulating fail bit counts, and updating the read bias when the absolute accumulator value exceeds a threshold, shifting the read bias in a correction direction based on the accumulator sign.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If read bias is fixed for memory blocks, then device complexity is reduced, but reliability deteriorates due to varying access frequencies and physical characteristics causing drift in read voltage threshold distributions

Engineering Contradiction:
Improveread operation reliabilityVSAvoidread bias tracking system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a feedback mechanism where the controller performs read operations using modified read biases, accumulates fail bit counts, and updates the read bias set based on the accumulator values. This closed-loop feedback system continuously adjusts read biases to track optimal values, resolving the contradiction between fixed simplicity and adaptive reliability.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent transforms the static read bias approach into a dynamic system where read biases are continuously adjusted based on accumulated fail bit counts. The read bias set evolves over time through updates triggered when accumulator values exceed thresholds, enabling the system to adapt to changing memory characteristics while maintaining operational reliability.

Inventive Principle:
Principle #15Dynamics

2Reliability

If read bias is frequently adjusted to track optimal values, then reliability is improved, but productivity deteriorates due to additional operations and processing overhead

Engineering Contradiction:
Improveread operation reliabilityVSAvoidread operation throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies partial action by updating read biases only when necessary - specifically when accumulator values exceed predefined thresholds. This selective update approach avoids unnecessary adjustments that would reduce productivity, while still maintaining reliability by making corrections when performance degradation is detected.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The system performs periodic accumulation of fail bit counts and updates read biases at intervals determined by threshold crossings rather than continuously. This periodic update mechanism balances reliability improvement with productivity preservation by limiting the frequency of bias adjustments to only when performance degradation is detected.

Inventive Principle:
Principle #19Periodic action

3Adaptability or versatility

If modification arrays are applied to read bias set, then adaptability is improved for tracking optimal read biases, but device complexity increases due to additional data structures and processing logic

Engineering Contradiction:
Improveread bias adaptation capabilityVSAvoidmodification array management complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments the read bias adjustment process into distinct components: the read bias set, multiple modification arrays, and an accumulation mechanism. Each modification array contains specific adjustment values that can be independently selected and applied, allowing fine-grained control over bias adjustments while organizing complexity into manageable segments.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by using different modification arrays for different read bias values and memory conditions. Each modification array is tailored with specific adjustment characteristics, allowing the system to apply locally optimized adjustments rather than uniform changes, thereby improving adaptability while managing complexity through specialized data structures.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11366718B2Optimal read bias tracking system and method thereof
Publication Date: 2022.06.21 SK HYNIX INC
  • US11366718B2 patent drawing
  • US11366718B2 patent drawing
  • US11366718B2 patent drawing

AI summary

A memory system includes a memory device including a plurality of cells associated with multiple pages and a controller. The controller selects a read bias set in response to a read address and modifies the read bias set to generate modified read bias set using one of a plurality of modification arrays. The controller performs a read operation on the select page using the modified read bias set. For a select read bias of the read bias set, the controller accumulates a fail bit count corresponding to a read operation using a select modified read bias of the modified read bias set into the plurality of accumulators using subtraction or addition. When an absolute value of a certain accumulator of the fail bit count is greater than a threshold, the controller shifts the select read bias in a correction direction by a specific magnitude corresponding to the accumulator sign.